Does VXOR.VX produce a vector mask?
No. It writes ordinary SEW-wide vector elements. Comparisons write mask results; VMXOR.MM performs logical XOR on one mask bit per element.
VXOR.VX
RISC-V VXOR.VX Instruction Details
Instruction ManualOPIVXVXOR.VX applies SEW-width integer bitwise XOR to active RVV elements.
Instruction Syntax
vxor.vx vd, vs2, rs1, vm
Operand Breakdown
vd, vs2: vector groups with EEW=SEW and EMUL=LMUL; active elements write SEW-bit XOR results, not mask results.
32-bit OP-V: opcode=1010111, funct6=001011, funct3=100 (OPIVX). vm is bit25, vs2 bits24:20, rs1 bits19:15, and vd bits11:7. vm is not a numeric assembly operand: optional v0.t means vm=0; omission means vm=1.
The second source x[rs1] supplies low SEW bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW; x0 always supplies zero. Active elements compute vs2[i] XOR scalar.
Equal-width source/destination overlap is legal. Register groups align to EMUL. Ordinary masked vd excludes v0, which cannot supply both an EEW=1 mask and data.
Require V 1.0, enabled vector state, vill=0, and support for selected SEW/EEW and EMUL. Active elements satisfy vstart<=i<vl with masking enabled. Prestart stays unchanged; inactive/tail follow vma/vta, allowing old values or all ones. vstart>=vl (including vl=0) updates no destination elements; success resets vstart=0. The animation fixes VLEN=4096, LMUL=m1, vstart=0; stages are not processor cycles.
VVector IntegerBitwise
Instruction Behavior
RISC-V VXOR.VX uses OP-V encoding and computes vs2 ^ the second source for each active element, writing vd. The second source is integer scalar register x[rs1] converted to a SEW-width element by the .vx rules; with vm=0, v0.t controls participating elements.
VXOR.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VXOR applies SEW-width bitwise XOR to active elements and writes vd.
Instruction input
vxor.vx
Teaching context: V 1.0, enabled vector state and valid supported vtype/SEW; LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Active elements compute vs2 XOR x[rs1]; take low SEW bits when XLEN>SEW, sign-extend when XLEN<SEW, and x0 supplies zero, writing SEW-bit ordinary vector elements. Equal-width source/destination overlap is legal; with v0.t, vd and data sources exclude v0. Only body is shown, without definite inactive/tail values; vma/vta apply. VL=0 updates no destination elements. Stages are teaching steps, not processor cycles.
Execution Context
OP-V encodingvxor.vx
funct6
001011
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
^
^
^
^
^
^
^
^
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vxor.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer bitwise XOR, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VXOR.VX is a V-extension single-width integer logical instruction: within vl, active elements compute vs2 ^ the second source, keep the SEW-bit result, and write ordinary vector register vd.
The OP-V opcode is 1010111. VXOR.VX uses funct6=001011, and the .vx form uses funct3=100.
The VX form reads x[rs1]: use its low SEW bits when XLEN>SEW, or sign-extend to SEW when XLEN<SEW; x0 always supplies zero.
Only body active elements execute; with vm=0, elements selected by v0.t participate, while masked-off and tail elements follow the current vma/vta policies.
The result is written to ordinary SEW-wide vector elements, rather than one comparison-mask bit per element.
Vector Execution Context
vd, vs2: vector groups with EEW=SEW and EMUL=LMUL; active elements write SEW-bit XOR results, not mask results.
32-bit OP-V: opcode=1010111, funct6=001011, funct3=100 (OPIVX). vm is bit25, vs2 bits24:20, rs1 bits19:15, and vd bits11:7. vm is not a numeric assembly operand: optional v0.t means vm=0; omission means vm=1.
The second source x[rs1] supplies low SEW bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW; x0 always supplies zero. Active elements compute vs2[i] XOR scalar.
Equal-width source/destination overlap is legal. Register groups align to EMUL. Ordinary masked vd excludes v0, which cannot supply both an EEW=1 mask and data.
Require V 1.0, enabled vector state, vill=0, and support for selected SEW/EEW and EMUL. Active elements satisfy vstart<=i<vl with masking enabled. Prestart stays unchanged; inactive/tail follow vma/vta, allowing old values or all ones. vstart>=vl (including vl=0) updates no destination elements; success resets vstart=0. The animation fixes VLEN=4096, LMUL=m1, vstart=0; stages are not processor cycles.
Common Usage Scenarios
toggling selected bits, combining parity patterns, or building per-element difference masks
Assume enabled V 1.0/vector state, valid supported e16,m1,tu,mu, VLEN=4096, vstart=0, supported source widths, and initialized sources/v0. vsetivli requests AVL=4, giving vl=4; v0.mask[0..3]=1011. vs2[0]=0x00f0, x11=0x000f → vd[0]=0x00ff; inactive lane1 and tails keep old destination values.
RVV per-element bit operations
Assume enabled V 1.0/vector state, valid supported e16,m1,tu,mu, VLEN=4096, vstart=0, supported source widths, and initialized sources/v0. vsetivli requests AVL=4, giving vl=4; v0.mask[0..3]=1011. vs2[0]=0x00f0, x11=0x000f → vd[0]=0x00ff; inactive lane1 and tails keep old destination values.
Pre-Use Checklist
Syntax Check
- vd, vs2: vector groups with EEW=SEW and EMUL=LMUL; active elements write SEW-bit XOR results, not mask results.
- 32-bit OP-V: opcode=1010111, funct6=001011, funct3=100 (OPIVX). vm is bit25, vs2 bits24:20, rs1 bits19:15, and vd bits11:7. vm is not a numeric assembly operand: optional v0.t means vm=0; omission means vm=1.
Semantic Check
- The second source x[rs1] supplies low SEW bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW; x0 always supplies zero. Active elements compute vs2[i] XOR scalar.
- Equal-width source/destination overlap is legal. Register groups align to EMUL. Ordinary masked vd excludes v0, which cannot supply both an EEW=1 mask and data.
- Require V 1.0, enabled vector state, vill=0, and support for selected SEW/EEW and EMUL. Active elements satisfy vstart<=i<vl with masking enabled. Prestart stays unchanged; inactive/tail follow vma/vta, allowing old values or all ones. vstart>=vl (including vl=0) updates no destination elements; success resets vstart=0. The animation fixes VLEN=4096, LMUL=m1, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
VXOR.VX writes ordinary vector elements. It does not produce a comparison mask and is not the same as VMXOR.MM mask-register logic.
The related VI form uses a 5-bit signed immediate in -16..15; larger constants normally come from an integer register through the .vx form.
Masked-off and tail elements follow the current vtype vma/vta policies; do not assume fixed zeroing or fixed preservation.
FAQ
What determines the element width for VXOR.VX?
The vtype SEW determines element width. Body elements satisfy vstart≤i<vl; only mask-enabled body elements perform the operation.
How does VXOR.VX handle v0.t zero bits when vm=0?
Those elements do not execute this logical operation. The destination element follows the current mask policy, so the mnemonic does not imply a fixed zero result.