Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VXOR.VX
RISC-V VXOR.VX Instruction Details
Instruction ManualV-typeVXOR.VX applies SEW-width integer bitwise XOR to active RVV elements.
Instruction Syntax
vxor.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector IntegerBitwise
Instruction Behavior
RISC-V VXOR.VX uses OP-V encoding and computes vs2 ^ the second source for each active element, writing vd. The second source is integer scalar register x[rs1] converted to a SEW-width element by the .vx rules; with vm=0, v0.t controls participating elements.
VXOR.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VXOR applies SEW-width bitwise XOR to active elements and writes vd.
Instruction input
vxor.vx
OP-V encodingvxor.vx
funct6
001011
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
^
^
^
^
^
^
^
^
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vxor.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer bitwise XOR, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VXOR.VX is a V-extension single-width integer logical instruction: within vl, active elements compute vs2 ^ the second source, keep the SEW-bit result, and write ordinary vector register vd.
The OP-V opcode is 1010111. VXOR.VX uses funct6=001011, and the .vx form uses funct3=100.
The VX form reads scalar x[rs1] and converts it to a SEW-width element by the .vx rules before the operation.
Only body active elements execute; with vm=0, elements selected by v0.t participate, while masked-off and tail elements follow the current vma/vta policies.
The result is an ordinary SEW-width integer bit pattern and sets no condition code, integer exception flag, or floating-point fflags.
Vector Execution Context
When reading VXOR.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
toggling selected bits, combining parity patterns, or building per-element difference masks
e.g., sub t0, a0, a1 — compute the difference a0 - a1.
RVV per-element bit operations
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vxor.vx v4, v8, a1, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
VXOR.VX writes ordinary vector elements. It does not produce a comparison mask and is not the same as VMXOR.MM mask-register logic.
The related VI form uses a 5-bit signed immediate in -16..15; larger constants normally come from an integer register through the .vx form.
Masked-off and tail elements follow the current vtype vma/vta policies; do not assume fixed zeroing or fixed preservation.
FAQ
Does VXOR.VX produce a vector mask?
No. VXOR.VX writes ordinary vector elements; compare instructions produce mask results, and mask-register logic uses .mm instructions.
What determines the element width for VXOR.VX?
The current vtype SEW determines element width; VL determines the number of body elements for this instruction. They are different concepts.
How does VXOR.VX handle v0.t zero bits when vm=0?
Those elements do not execute this logical operation. The destination element follows the current mask policy, so the mnemonic does not imply a fixed zero result.