Does VXOR.VI produce a vector mask?
No. VXOR.VI writes ordinary SEW-width vector elements; VMXOR.MM applies logic to one mask bit per element index.
VXOR.VI
RISC-V VXOR.VI Instruction Details
Instruction ManualV-typeVXOR.VI applies SEW-width integer bitwise XOR to active RVV elements.
Instruction Syntax
vxor.vi vd, vs2, imm, vm
Operand Breakdown
vd and vs2 have EEW=SEW and EMUL=LMUL. The second source imm is a 5-bit signed immediate in -16..15, sign-extended to SEW.
32-bit OP-V: opcode=1010111, funct6=001011, funct3=011 (OPIVI); vm bit25, vs2 bits24:20, imm[4:0] bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Active elements compute vs2 XOR the sign-extended immediate and write SEW-bit results; imm=-1 inverts each bit. The result is ordinary vector data, not a mask.
Equal-width source/destination overlap is legal. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
VVector IntegerBitwise
Extension condition: RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW.
Instruction Behavior
RISC-V VXOR.VI uses OP-V encoding and computes vs2 ^ the second source for each active element, writing vd. The second source is the 5-bit signed immediate sign-extended to SEW; with vm=0, v0.t controls participating elements.
VXOR.VI Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VXOR applies SEW-width bitwise XOR to active elements and writes vd.
Instruction input
vxor.vi
Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Enter nonnegative bit patterns. Require support for the selected SEW; imm is a 5-bit signed immediate in -16..15, sign-extended to SEW before bitwise XOR with vs2. Equal-width source/destination overlap is legal; the result is not a mask. With v0.t, vd and data sources exclude v0. Only body is shown; inactive/tail follow vma/vta without definite displayed values. VL=0 updates nothing; success resets vstart=0. Stages are teaching steps, not processor cycles.
Execution Context
immediate value
-1 -> 0xffff
5-bit signed imm is sign-extended to SEWOP-V encodingvxor.vi
funct6
001011
vm
0
vs2
01000
simm5
11111
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
^
^
^
^
^
^
^
^
imm
0xffff
0xffff
0xffff
0xffff
0xffff
0xffff
0xffff
0xffff
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vxor.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer bitwise XOR, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VXOR.VI is a V-extension single-width integer logical instruction: within vl, active elements compute vs2 ^ the second source, keep the SEW-bit result, and write ordinary vector register vd.
The OP-V opcode is 1010111. VXOR.VI uses funct6=001011, and the .vi form uses funct3=011.
The VI form sign-extends the 5-bit signed immediate to SEW before using it as the second source for each element.
Only body active elements execute; with vm=0, elements selected by v0.t participate, while masked-off and tail elements follow the current vma/vta policies.
The result is an ordinary SEW-width integer bit pattern; imm=-1 inverts each bit and does not produce a comparison mask.
Vector Execution Context
vd and vs2 have EEW=SEW and EMUL=LMUL. The second source imm is a 5-bit signed immediate in -16..15, sign-extended to SEW.
32-bit OP-V: opcode=1010111, funct6=001011, funct3=011 (OPIVI); vm bit25, vs2 bits24:20, imm[4:0] bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Active elements compute vs2 XOR the sign-extended immediate and write SEW-bit results; imm=-1 inverts each bit. The result is ordinary vector data, not a mask.
Equal-width source/destination overlap is legal. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Common Usage Scenarios
toggling selected bits, combining parity patterns, or building per-element difference masks
Assume RV32/RV64 V 1.0, enabled vector state, valid supported e16,m1,ta,ma, XLEN=64, VLEN=4096, vl=4, vstart=0, initialized sources, and v0.mask[0..3]=1111. vs2[0]=0x00f0, imm=-1 → vd[0]=0xff0f; other active elements follow the same rule and tails are agnostic, allowing old values or all ones. Success resets vstart=0.
RVV per-element bit operations
Assume RV32/RV64 V 1.0, enabled vector state, valid supported e16,m1,ta,ma, XLEN=64, VLEN=4096, vl=4, vstart=0, initialized sources, and v0.mask[0..3]=1111. vs2[0]=0x00f0, imm=-1 → vd[0]=0xff0f; other active elements follow the same rule and tails are agnostic, allowing old values or all ones. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd and vs2 have EEW=SEW and EMUL=LMUL. The second source imm is a 5-bit signed immediate in -16..15, sign-extended to SEW.
- 32-bit OP-V: opcode=1010111, funct6=001011, funct3=011 (OPIVI); vm bit25, vs2 bits24:20, imm[4:0] bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Active elements compute vs2 XOR the sign-extended immediate and write SEW-bit results; imm=-1 inverts each bit. The result is ordinary vector data, not a mask.
- Equal-width source/destination overlap is legal. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
- RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
VXOR.VI writes ordinary vector elements. It does not produce a comparison mask and is not the same as VMXOR.MM mask-register logic.
VXOR.VI imm is a 5-bit signed immediate in -16..15 and is sign-extended to SEW; it is not an arbitrary-width bit mask.
Masked-off and tail elements follow the current vtype vma/vta policies; do not assume fixed zeroing or fixed preservation.
FAQ
What determines the element width for VXOR.VI?
The current vtype SEW determines element width; body elements satisfy vstart<=i<vl, with vl as the upper bound rather than a count independent of vstart.
How does VXOR.VI handle v0.t zero bits when vm=0?
Those elements do not execute this logical operation. The destination element follows the current mask policy, so the mnemonic does not imply a fixed zero result.