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VXOR.VI

RISC-V VXOR.VI Instruction Details

Instruction ManualI-type

VXOR.VI performs bitwise XOR on vector elements.

Instruction Syntax

vxor.vi vd, vs2, imm, vm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
VVector Operations
Related Search Terms
vxor.vi instructionvxor vivxor.vi RVVvxor.vi vl vtypevector bitwise XORvxor.vi mask

Instruction Behavior

vxor.vi is a V extension integer logical instruction that computes element-wise XOR between vs2 and a sign-extended 5-bit immediate.

Quick Understanding & Search Notes

vxor.vi is a V extension vector instruction. Active elements are controlled by vl, vtype, vstart, and the optional v0.t mask; the immediate is sign-extended to SEW and then XOR is applied element-wise with vs2.

Official syntax is `vxor.vi vd, vs2, imm, vm`; without a mask operand it is unmasked, while `, v0.t` updates only selected active elements.
Tail elements and masked-off elements follow the current vtype tail/mask policy; the mnemonic alone does not imply zeroing.
For bitwise inversion, use the -1 immediate rather than an out-of-range mask constant.
RISC-V Unprivileged ISA Manual, V standard vector extension

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «vxor.vi v8, v12, -1, v0.t».

Data Storing

Understand this scenario with real code like «vxor.vi v8, v12, -1, v0.t».

Vector Operations

Understand this scenario with real code like «vxor.vi v8, v12, -1, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The vi immediate is a 5-bit signed immediate sign-extended to SEW.
The result width is SEW; this is not a widening operation.
Masked-off and tail elements follow the current policy.

FAQ

What determines the element count for vxor.vi?

The current vl and vtype determine it, with vstart, LMUL, SEW, mask state, and tail policy also affecting execution.

Does vxor.vi always process the whole vector register?

No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.