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VAND.VI

RISC-V VAND.VI Instruction Details

Instruction ManualV-type

VAND.VI applies SEW-width integer bitwise AND to active RVV elements.

Instruction Syntax

vand.vi vd, vs2, imm, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VVector IntegerBitwise

Related Search Terms

vand.vi instruction vand.vi syntax vand.vi encoding RISC-V vand.vi RVV bitwise AND vector immediate bitwise AND vand.vi mask

Instruction Behavior

RISC-V VAND.VI uses OP-V encoding and computes vs2 & the second source for each active element, writing vd. The second source is the 5-bit signed immediate sign-extended to SEW; with vm=0, v0.t controls participating elements.

VAND.VI Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VAND applies SEW-width bitwise AND to active elements and writes vd.

Instruction input

vand.vi

vdUse v0-v31vs2Use v0-v31immUse -16..15vmexecution mask control

VLSEWvs2 elementscomma-separated

immediate value

-16 -> 0xfff0

5-bit signed imm is sign-extended to SEW

v0 mask bitscontinuous 0/1 bit string

OP-V encodingvand.vi

funct6

001001

vs2

01000

simm5

10000

funct3

011

00100

opcode

1010111

lane

0x00fa

0x010b

0x011c

0x012d

0x013e

0x014f

0x0160

0x0171

imm

0xfff0

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vand.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer bitwise AND, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VAND.VI is a V-extension single-width integer logical instruction: within vl, active elements compute vs2 & the second source, keep the SEW-bit result, and write ordinary vector register vd.

The OP-V opcode is 1010111. VAND.VI uses funct6=001001, and the .vi form uses funct3=011.

The VI form sign-extends the 5-bit signed immediate to SEW before using it as the second source for each element.

Only body active elements execute; with vm=0, elements selected by v0.t participate, while masked-off and tail elements follow the current vma/vta policies.

The result is an ordinary SEW-width integer bit pattern and sets no condition code, integer exception flag, or floating-point fflags.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VAND.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

keeping selected bits, clearing bit fields, or combining per-element bit masks

Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vand.vi v4, v8, -16, v0.t».

RVV per-element bit operations

Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vand.vi v4, v8, -16, v0.t».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is V-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

VAND.VI writes ordinary vector elements. It does not produce a comparison mask and is not the same as VMAND.MM mask-register logic.

VAND.VI imm is a 5-bit signed immediate in -16..15 and is sign-extended to SEW; it is not an arbitrary-width bit mask.

Masked-off and tail elements follow the current vtype vma/vta policies; do not assume fixed zeroing or fixed preservation.

FAQ

Does VAND.VI produce a vector mask?

No. VAND.VI writes ordinary vector elements; compare instructions produce mask results, and mask-register logic uses .mm instructions.

What determines the element width for VAND.VI?

The current vtype SEW determines element width; VL determines the number of body elements for this instruction. They are different concepts.

How does VAND.VI handle v0.t zero bits when vm=0?

Those elements do not execute this logical operation. The destination element follows the current mask policy, so the mnemonic does not imply a fixed zero result.