Does VOR.VI produce a vector mask?
No. VOR.VI writes ordinary vector elements; compare instructions produce mask results, and mask-register logic uses .mm instructions.
VOR.VI
RISC-V VOR.VI Instruction Details
Instruction ManualOPIVI (OP-V)VOR.VI applies SEW-width integer bitwise OR to active RVV elements.
Instruction Syntax
vor.vi vd, vs2, imm, vm
Operand Breakdown
Syntax: vor.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=001010, funct3=011.
vd, vs2 and a vector second source are ordinary SEW/LMUL groups. Active elements compute vs2[i] | second source, not .mm mask logic. Same-width source/destination overlap is allowed; equal sources read equal initial values.
imm is a signed 5-bit immediate in -16–15, sign-extended to SEW; imm=-1 sets every active result bit to 1.
Group starts align to EMUL, with EMUL≤8; masked vd cannot contain v0. When v0 supplies the EEW=1 execution mask, it cannot also supply SEW source data.
Require V 1.0, enabled vector state and valid supported vtype. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements. Masked vd cannot contain v0, which cannot supply both mask and data.
VVector IntegerBitwise
Instruction Behavior
RISC-V VOR.VI uses OP-V encoding and computes vs2 | the second source for each active element, writing vd. The second source is the 5-bit signed immediate sign-extended to SEW; with vm=0, v0.t controls participating elements.
VOR.VI Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VOR applies SEW-width bitwise OR to active elements and writes vd.
Instruction input
vor.vi
Execution Context
immediate value
7 -> 0x0007
5-bit signed imm is sign-extended to SEWThe teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvor.vi
funct6
001010
vm
0
vs2
01000
simm5
00111
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
|
|
|
|
|
|
|
|
imm
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vor.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer bitwise OR, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VOR.VI is a V-extension single-width integer logical instruction: within vl, active elements compute vs2 | the second source, keep the SEW-bit result, and write ordinary vector register vd.
The OP-V opcode is 1010111. VOR.VI uses funct6=001010, and the .vi form uses funct3=011.
The VI form sign-extends the 5-bit signed immediate to SEW before using it as the second source for each element.
Only body active elements execute; with vm=0, elements selected by v0.t participate, while masked-off and tail elements follow the current vma/vta policies.
The result is an ordinary SEW-width integer bit pattern, not a one-bit-per-element destination mask.
Vector Execution Context
Syntax: vor.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=001010, funct3=011.
vd, vs2 and a vector second source are ordinary SEW/LMUL groups. Active elements compute vs2[i] | second source, not .mm mask logic. Same-width source/destination overlap is allowed; equal sources read equal initial values.
imm is a signed 5-bit immediate in -16–15, sign-extended to SEW; imm=-1 sets every active result bit to 1.
Group starts align to EMUL, with EMUL≤8; masked vd cannot contain v0. When v0 supplies the EEW=1 execution mask, it cannot also supply SEW source data.
Require V 1.0, enabled vector state and valid supported vtype. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements. Masked vd cannot contain v0, which cannot supply both mask and data.
Common Usage Scenarios
setting selected bits, combining bit fields, or merging per-element data bit patterns
Assume enabled V/VS, valid m1, VLEN≥128, supported operand widths, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. a0=4, SEW=16, v8=[250,267,284,301], imm=7 → v4=[255,271,287,303]. Bitwise OR keeps SEW bits. Inactive/tail follow policy without assumed zeroing.
RVV per-element bit operations
Assume enabled V/VS, valid m1, VLEN≥128, supported operand widths, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. a0=4, SEW=16, v8=[250,267,284,301], imm=7 → v4=[255,271,287,303]. Bitwise OR keeps SEW bits. Inactive/tail follow policy without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vor.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=001010, funct3=011.
- vd, vs2 and a vector second source are ordinary SEW/LMUL groups. Active elements compute vs2[i] | second source, not .mm mask logic. Same-width source/destination overlap is allowed; equal sources read equal initial values.
Semantic Check
- imm is a signed 5-bit immediate in -16–15, sign-extended to SEW; imm=-1 sets every active result bit to 1.
- Group starts align to EMUL, with EMUL≤8; masked vd cannot contain v0. When v0 supplies the EEW=1 execution mask, it cannot also supply SEW source data.
- Require V 1.0, enabled vector state and valid supported vtype. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements. Masked vd cannot contain v0, which cannot supply both mask and data.
Pitfalls / Common Confusions
VOR.VI writes ordinary vector elements. It does not produce a comparison mask and is not the same as VMOR.MM mask-register logic.
VOR.VI imm is a 5-bit signed immediate in -16..15 and is sign-extended to SEW; it is not an arbitrary-width bit mask.
Masked-off and tail elements follow the current vtype vma/vta policies; do not assume fixed zeroing or fixed preservation.
FAQ
What determines the element width for VOR.VI?
The current vtype SEW determines element width; body elements satisfy vstart≤i<vl. Element width and execution range are different concepts.
How does VOR.VI handle v0.t zero bits when vm=0?
Those elements do not execute this logical operation. The destination element follows the current mask policy, so the mnemonic does not imply a fixed zero result.