Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFMACC.VV
RISC-V VFMACC.VV Instruction Details
Instruction ManualV-typeFloating-point fused multiply-add: vd[i] = +(vs1[i] * vs2[i]) + vd[i].
Instruction Syntax
vfmacc.vv vd, vs1, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Multiply-AddFloating-Point
Instruction Behavior
VFMACC.VV follows the official RVV FMA formula: vd[i] = +(vs1[i] * vs2[i]) + vd[i]. The multiply and add are fused with one rounding and no intermediate rounded product; vd is a read/write accumulator. Vector floating-point operations require base scalar floating-point extensions corresponding to the supported vector element widths; an encoding is reserved when an FP operand EEW does not correspond to a supported IEEE-754-compatible type.
VFMACC.VV Decode And Execute Animation
Decode the OP-V encoding and execute fused multiply-accumulate lane by lane: each active lane multiplies vs1[i] and vs2[i], then adds old vd[i] with one rounding.
Instruction input
vfmacc.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xb0861257
31..26
25
24..20
19..15
14..12
11..7
6..0
101100
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma(1, 0.5, 0.5) -> 1
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma(1, 0.5, 0.5)
1
i=1active
fma(1.5, 1, -1)
0.5
i=2skip
v0.t=0, not executed
--
i=3active
fma(2.5, 2, -2.5)
2.5
i=4active
fma(-3, 2.5, 4)
-3.5
i=5active
fma(3.5, 3, -4.5)
6
i=6skip
v0.t=0, not executed
--
i=7active
fma(4.5, 4, -8.5)
9.5
In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, (vs1 * vs2) + old vd is fused in each active lane and rounded only once to the current SEW. The animation explicitly reads old vd; finite inputs use exact binary intermediates so a pre-rounded product is not presented as architectural state. The real instruction uses dynamic frm; use of an invalid frm is reserved even when VL=0 or no elements are active. NaNs, infinities, and accrued fflags remain governed by the official RVV FP rules.
Quick Understanding & Search Notes
The key facts for VFMACC.VV are the official FMA formula vd[i] = +(vs1[i] * vs2[i]) + vd[i] and single-rounding semantics.
In accumulate forms, vd is a read/write accumulator.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, fixed-point vxrm does not control these instructions, and use of an invalid frm is reserved.
Vector floating-point operations require base scalar floating-point extensions corresponding to the supported vector element widths; an encoding is reserved when an FP operand EEW does not correspond to a supported IEEE-754-compatible type. Execution with mstatus.FS Off raises an illegal-instruction exception; FP exceptions from active elements accrue in fflags, while inactive elements do not.
Vector Execution Context
When reading VFMACC.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Matrix Multiply
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmacc.vv v1, v2, v3 # vd[i] = +(vs1[i] * vs2[i]) + vd[i]».
Signal Processing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmacc.vv v1, v2, v3 # vd[i] = +(vs1[i] * vs2[i]) + vd[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Use the formula vd[i] = +(vs1[i] * vs2[i]) + vd[i]; do not swap the roles of vs2, vs1, or the old vd value.
This is a fused operation, not a separately rounded multiply followed by add.
The encoding is reserved when an FP operand EEW does not correspond to a supported IEEE-754-compatible type.
FAQ
Do these instructions use vxrm?
No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.