Do these instructions use vxrm?
No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFMACC.VF
RISC-V VFMACC.VF Instruction Details
Instruction ManualV-typeFloating-point fused multiply-add: vd[i] = +(f[rs1] * vs2[i]) + vd[i].
Instruction Syntax
vfmacc.vf vd, rs1, vs2, vm
Operand Breakdown
Ternary assembly order is vd, rs1, vs2, vm. vd also supplies an old input; same-width registers may overlap, and equal registers read equal initial values.
rs1 selects FP f0–f31 or an ABI name. With FLEN>SEW, an invalid NaN box supplies canonical NaN; FLEN<SEW encodings are reserved.
Compute (vs1[i] or f[rs1])×vs2[i]+old vd[i], overwriting the addend. The fused result rounds only once by frm; vxrm is not used.
Require V, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or vstart≥vl.
Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) compute. Inactive/tail values follow vma/vta; prestart is unchanged. vl=0 or vstart≥vl leaves the destination unchanged.
vm is optional v0.t. Masked vd cannot overlap v0, and v0 cannot supply both an EEW=1 mask and SEW data. Only active-element exceptions accrue in fflags. The animation fixes a finite RNE path.
VVector Multiply-AddFloating-Point
Instruction Behavior
VFMACC.VF follows the official RVV FMA formula: vd[i] = +(f[rs1] * vs2[i]) + vd[i]. The multiply and add are fused with one rounding and no intermediate rounded product; vd is a read/write accumulator. Vector floating-point operations require base scalar floating-point extensions corresponding to the supported vector element widths; an encoding is reserved when an FP operand EEW does not correspond to a supported IEEE-754-compatible type.
VFMACC.VF Decode And Execute Animation
Decode the OP-V encoding and execute fused multiply-accumulate lane by lane: each active lane multiplies f[rs1] and vs2[i], then adds old vd[i] with one rounding.
Instruction input
vfmacc.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xb0855257
31..26
25
24..20
19..15
14..12
11..7
6..0
101100
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma(1, 1.5, 0.5) -> 2
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma(1, 1.5, 0.5)
2
i=1active
fma(1.5, 1.5, -1)
1.25
i=2skip
v0.t=0, not executed
--
i=3active
fma(2.5, 1.5, -2.5)
1.25
i=4active
fma(-3, 1.5, 4)
-0.5
i=5active
fma(3.5, 1.5, -4.5)
0.75
i=6skip
v0.t=0, not executed
--
i=7active
fma(4.5, 1.5, -8.5)
-1.75
In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, (f[rs1] * vs2[i]) + old vd[i] is fused in each active lane and rounded only once to the current SEW. The animation explicitly reads old vd; finite inputs use exact binary intermediates so a pre-rounded product is not presented as architectural state. The real instruction uses dynamic frm; use of an invalid frm is reserved even when VL=0 or no elements are active. NaNs, infinities, and accrued fflags remain governed by the official RVV FP rules.
Old vd is the addend. Equal vector registers must have equal initial bits. VF scalars are read at FLEN=64, with valid NaN-boxing assumed for SEW=32; this animation computes finite RNE results without displaying fflags.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, and supported SEW. FP inputs are first represented as binary32/64. VL=0 updates no destination elements; same-width source/destination overlap is allowed. Inactive and tail values follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
The key facts for VFMACC.VF are the official FMA formula vd[i] = +(f[rs1] * vs2[i]) + vd[i] and single-rounding semantics.
In accumulate forms, vd is a read/write accumulator.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, fixed-point vxrm does not control these instructions, and use of an invalid frm is reserved.
Vector floating-point operations require base scalar floating-point extensions corresponding to the supported vector element widths; an encoding is reserved when an FP operand EEW does not correspond to a supported IEEE-754-compatible type. Execution with mstatus.FS Off raises an illegal-instruction exception; FP exceptions from active elements accrue in fflags, while inactive elements do not.
Vector Execution Context
Ternary assembly order is vd, rs1, vs2, vm. vd also supplies an old input; same-width registers may overlap, and equal registers read equal initial values.
rs1 selects FP f0–f31 or an ABI name. With FLEN>SEW, an invalid NaN box supplies canonical NaN; FLEN<SEW encodings are reserved.
Compute (vs1[i] or f[rs1])×vs2[i]+old vd[i], overwriting the addend. The fused result rounds only once by frm; vxrm is not used.
Require V, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or vstart≥vl.
Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) compute. Inactive/tail values follow vma/vta; prestart is unchanged. vl=0 or vstart≥vl leaves the destination unchanged.
vm is optional v0.t. Masked vd cannot overlap v0, and v0 cannot supply both an EEW=1 mask and SEW data. Only active-element exceptions accrue in fflags. The animation fixes a finite RNE path.
Common Usage Scenarios
Fused FP Accumulation
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked and VF scalars are validly NaN-boxed. old v1=[1,2,-3,4], v2=[2,4,-2,0], ft0=1.5 → v1=[4,8,-6,4]. Results round only once; tails follow ta without assumed zeroing.
Masked Element Multiply-Add
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked and VF scalars are validly NaN-boxed. old v1=[1,2,-3,4], v2=[2,4,-2,0], ft0=1.5 → v1=[4,8,-6,4]. Results round only once; tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Ternary assembly order is vd, rs1, vs2, vm. vd also supplies an old input; same-width registers may overlap, and equal registers read equal initial values.
- rs1 selects FP f0–f31 or an ABI name. With FLEN>SEW, an invalid NaN box supplies canonical NaN; FLEN<SEW encodings are reserved.
Semantic Check
- Compute (vs1[i] or f[rs1])×vs2[i]+old vd[i], overwriting the addend. The fused result rounds only once by frm; vxrm is not used.
- Require V, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or vstart≥vl.
- Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) compute. Inactive/tail values follow vma/vta; prestart is unchanged. vl=0 or vstart≥vl leaves the destination unchanged.
- vm is optional v0.t. Masked vd cannot overlap v0, and v0 cannot supply both an EEW=1 mask and SEW data. Only active-element exceptions accrue in fflags. The animation fixes a finite RNE path.
Pitfalls / Common Confusions
Use the formula vd[i] = +(f[rs1] * vs2[i]) + vd[i]; do not swap the roles of vs2, f[rs1], or the old vd value.
This is a fused operation, not a separately rounded multiply followed by add.
The encoding is reserved when an FP operand EEW does not correspond to a supported IEEE-754-compatible type.