Do these instructions use vxrm?
No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFNMACC.VF
RISC-V VFNMACC.VF Instruction Details
Instruction ManualR-typeFloating-point fused multiply-add/subtract: vd[i] = -(f[rs1] * vs2[i]) - vd[i].
Instruction Syntax
vfnmacc.vf vd, rs1, vs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector Multiply-AddFloating-Point
Instruction Behavior
VFNMACC.VF follows the official RVV FMA formula: vd[i] = -(f[rs1] * vs2[i]) - vd[i]. The multiply and add/subtract are fused with one rounding and no intermediate rounded product; vd is a read/write accumulator. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Quick Understanding & Search Notes
The key facts for VFNMACC.VF are the official FMA formula vd[i] = -(f[rs1] * vs2[i]) - vd[i] and single-rounding semantics.
In accumulate forms, vd is a read/write accumulator.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, and fixed-point vxrm does not control these instructions.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Common Usage Scenarios
Alternating Add/Sub
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfnmacc.vf v1, ft0, v2 # vd[i] = -(f[rs1] * vs2[i]) - vd[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Use the formula vd[i] = -(f[rs1] * vs2[i]) - vd[i]; do not swap the roles of vs2, vs1, f[rs1], or the old vd value.
This is fused operation, not a separately rounded multiply followed by add/subtract.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.