Do these instructions use vxrm?
No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFNMACC.VF
RISC-V VFNMACC.VF Instruction Details
Instruction ManualOPFVFFor each active element, fuse vd[i] = -(f[rs1] * vs2[i]) - old vd[i] with one final rounding.
Instruction Syntax
vfnmacc.vf vd, rs1, vs2[, v0.t]
Operand Breakdown
Syntax is vd, rs1, vs2[, v0.t]; the formula is -(f[rs1] * vs2[i]) - old vd[i]. Old vd is the subtrahend. Read all three inputs before one fused dynamic-frm rounding. funct6=101101, funct3=101, opcode=1010111; the instruction is 32 bits.
Vector operands and results are SEW bits, EMUL=LMUL. Same-width source/destination overlap is legal; equal registers require equal initial bits. rs1 encodes an FP f register. With FLEN>SEW a valid NaN box supplies the low SEW bits, while an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; data sources cannot read v0 at both data EEW and mask EEW=1.
Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Negate the product before subtracting the other term; a multiply with an already rounded product followed by add/subtract is not equivalent. Only active-element exceptions accrue in fflags. The animation covers finite binary32/64 RNE results, excluding NaNs, infinities, overflow, and full fflags.
V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D; SEW=16 arithmetic requires Zvfh. The animation fixes LMUL=m1, VLEN=4096, vstart=0, and FLEN=64.
Valid vtype, supported FP widths, and enabled VS/FS are required; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or with no active elements. vxrm does not control FP operations. Teaching steps are not processor cycles.
VVector Multiply-AddFloating-Point
Instruction Behavior
VFNMACC.VF computes vd[i] = -(f[rs1] * vs2[i]) - old vd[i] for active elements. Old vd is the subtrahend and needs an initial value. Multiplication and subtraction fuse with one dynamic-frm rounding, without rounding the product first. V FP32/FP64 paths depend on F/D; SEW=16 arithmetic requires Zvfh.
VFNMACC.VF Decode And Execute Animation
Decode OP-V and execute the negated fused operation: each active element computes -(f[rs1] * vs2[i]) - old vd[i]. Read old vd first, with no intermediate product rounding and one final RNE rounding.
Instruction input
vfnmacc.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xb4855257
31..26
25
24..20
19..15
14..12
11..7
6..0
101101
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma(-(1), 1.5, -(0.5)) -> -2
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma(-(1), 1.5, -(0.5))
-2
i=1active
fma(-(1.5), 1.5, -(-1))
-1.25
i=2skip
v0.t=0, not executed
--
i=3active
fma(-(2.5), 1.5, -(-2.5))
-1.25
i=4active
fma(-(-3), 1.5, -(4))
0.5
i=5active
fma(-(3.5), 1.5, -(-4.5))
-0.75
i=6skip
v0.t=0, not executed
--
i=7active
fma(-(4.5), 1.5, -(-8.5))
1.75
In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, -(f[rs1] * vs2[i]) - old vd[i] is fused in each active lane and rounded only once to the current SEW. The animation explicitly reads old vd; finite inputs use exact binary intermediates so a pre-rounded product is not presented as architectural state. The real instruction uses dynamic frm; use of an invalid frm is reserved even when VL=0 or no elements are active. NaNs, infinities, and accrued fflags remain governed by the official RVV FP rules.
Old vd is the subtrahend. Equal vector registers must have equal initial bits. VF scalars are read at FLEN=64, with valid NaN-boxing assumed for SEW=32; this animation computes finite RNE results without displaying fflags.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, and supported SEW. FP inputs are first represented as binary32/64. VL=0 updates no destination elements; same-width source/destination overlap is allowed. Inactive and tail values follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
Read old vd first: this instruction computes -(f[rs1] * vs2[i]) - old vd[i]. VFNMADD instead uses old vd as a multiplicand.
In accumulate forms, vd is a read/write accumulator.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, and fixed-point vxrm does not control these instructions.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Vector Execution Context
Syntax is vd, rs1, vs2[, v0.t]; the formula is -(f[rs1] * vs2[i]) - old vd[i]. Old vd is the subtrahend. Read all three inputs before one fused dynamic-frm rounding. funct6=101101, funct3=101, opcode=1010111; the instruction is 32 bits.
Vector operands and results are SEW bits, EMUL=LMUL. Same-width source/destination overlap is legal; equal registers require equal initial bits. rs1 encodes an FP f register. With FLEN>SEW a valid NaN box supplies the low SEW bits, while an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; data sources cannot read v0 at both data EEW and mask EEW=1.
Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Negate the product before subtracting the other term; a multiply with an already rounded product followed by add/subtract is not equivalent. Only active-element exceptions accrue in fflags. The animation covers finite binary32/64 RNE results, excluding NaNs, infinities, overflow, and full fflags.
V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D; SEW=16 arithmetic requires Zvfh. The animation fixes LMUL=m1, VLEN=4096, vstart=0, and FLEN=64.
Valid vtype, supported FP widths, and enabled VS/FS are required; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or with no active elements. vxrm does not control FP operations. Teaching steps are not processor cycles.
Common Usage Scenarios
Fused evaluation with both product and other term negated
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Vector inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes the example unmasked: old v1=[5,5,5,5], ft0=4, v2=[3,3,3,3] → v1=[-17,-17,-17,-17]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax is vd, rs1, vs2[, v0.t]; the formula is -(f[rs1] * vs2[i]) - old vd[i]. Old vd is the subtrahend. Read all three inputs before one fused dynamic-frm rounding. funct6=101101, funct3=101, opcode=1010111; the instruction is 32 bits.
- Vector operands and results are SEW bits, EMUL=LMUL. Same-width source/destination overlap is legal; equal registers require equal initial bits. rs1 encodes an FP f register. With FLEN>SEW a valid NaN box supplies the low SEW bits, while an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Semantic Check
- Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; data sources cannot read v0 at both data EEW and mask EEW=1.
- Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- Negate the product before subtracting the other term; a multiply with an already rounded product followed by add/subtract is not equivalent. Only active-element exceptions accrue in fflags. The animation covers finite binary32/64 RNE results, excluding NaNs, infinities, overflow, and full fflags.
- V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D; SEW=16 arithmetic requires Zvfh. The animation fixes LMUL=m1, VLEN=4096, vstart=0, and FLEN=64.
- Valid vtype, supported FP widths, and enabled VS/FS are required; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or with no active elements. vxrm does not control FP operations. Teaching steps are not processor cycles.
Pitfalls / Common Confusions
Use the formula vd[i] = -(f[rs1] * vs2[i]) - vd[i]; do not swap the roles of vs2, vs1, f[rs1], or the old vd value.
This is a fused operation, not a separately rounded multiply followed by add/subtract.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
FAQ
Does old vd have the same role in VFNMACC and VFNMADD?
No. VFNMACC computes −(source1×vs2)−old vd; VFNMADD computes −(source1×old vd)−vs2. Both negate the product, subtract the other term, and round only once after the fused calculation.