What input does old vd supply?
Old vd is the minuend. This instruction computes -(f[rs1] * vs2[i]) + old vd[i], so the destination is also an input.
VFNMSAC.VF
RISC-V VFNMSAC.VF Instruction Details
Instruction ManualOPFVFActive elements compute vd[i] = -(f[rs1] * vs2[i]) + old vd[i]; old vd is the minuend, with one dynamic-frm rounding.
Instruction Syntax
vfnmsac.vf vd, rs1, vs2, vm
Operand Breakdown
Syntax is vd, rs1, vs2[, v0.t]; compute -(f[rs1] * vs2[i]) + old vd[i]. Old vd is the minuend. Read all three inputs before one fused dynamic-frm rounding. funct6=101111, funct3=101, opcode=1010111; the instruction is 32 bits.
Vector operands and results are SEW bits, EMUL=LMUL. Same-width source/destination overlap is legal; equal registers require equal initial bits. rs1 selects an FP f register. With FLEN>SEW a valid NaN box supplies the low SEW bits, while an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; sources cannot read v0 at both data EEW and mask EEW=1.
Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Negate the product. A separately rounded multiply followed by add/subtract, or negating a previously computed final sum, is not equivalent. Only active-element FP exceptions accrue in fflags; vxrm is not used.
V 1.0 applies to RV32/RV64, supports FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0.
The animation fixes VLEN=4096, LMUL=m1, vstart=0, frm=RNE, FLEN=64, and ta/ma. It calculates finite binary32/64 results, assuming valid NaN-boxing for VF at SEW=32. NaNs, infinities, overflow, and full fflags are outside this model. Teaching steps are not processor cycles.
VVector Multiply-AddFloating-Point
Instruction Behavior
VFNMSAC.VF fuses a negated product with the other term for each active element. Old vd is the minuend and an input. Only the final result rounds, using dynamic frm.
VFNMSAC.VF Decode And Execute Animation
Decode the OP-V encoding and execute negated fused multiply-subtract-accumulate lane by lane: each active lane negates the product of f[rs1] and vs2[i], then adds old vd[i] with one rounding.
Instruction input
vfnmsac.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xbc855257
31..26
25
24..20
19..15
14..12
11..7
6..0
101111
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma(-(1), 1.5, 0.5) -> -1
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma(-(1), 1.5, 0.5)
-1
i=1active
fma(-(1.5), 1.5, -1)
-3.25
i=2skip
v0.t=0, not executed
--
i=3active
fma(-(2.5), 1.5, -2.5)
-6.25
i=4active
fma(-(-3), 1.5, 4)
8.5
i=5active
fma(-(3.5), 1.5, -4.5)
-9.75
i=6skip
v0.t=0, not executed
--
i=7active
fma(-(4.5), 1.5, -8.5)
-15.25
In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, -(f[rs1] * vs2[i]) + old vd[i] is fused in each active lane and rounded only once to the current SEW. The animation explicitly reads old vd; finite inputs use exact binary intermediates so a pre-rounded product is not presented as architectural state. The real instruction uses dynamic frm; use of an invalid frm is reserved even when VL=0 or no elements are active. NaNs, infinities, and accrued fflags remain governed by the official RVV FP rules.
Old vd is the minuend. Equal vector registers must have equal initial bits. VF scalars are read at FLEN=64, with valid NaN-boxing assumed for SEW=32; this animation computes finite RNE results without displaying fflags.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, and supported SEW. FP inputs are first represented as binary32/64. VL=0 updates no destination elements; same-width source/destination overlap is allowed. Inactive and tail values follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
Old vd is the minuend: vd[i] = -(f[rs1] * vs2[i]) + old vd[i], with one fused dynamic-frm rounding.
V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D; SEW=16 arithmetic requires Zvfh.
Require valid vtype, supported FP widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS also apply.
The optional vm assembly operand is v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled.
Prestart is unchanged; other inactive/tail elements follow vma/vta. Successful execution resets vstart=0. Invalid frm use is reserved, including at vl=0.
Vector Execution Context
Syntax is vd, rs1, vs2[, v0.t]; compute -(f[rs1] * vs2[i]) + old vd[i]. Old vd is the minuend. Read all three inputs before one fused dynamic-frm rounding. funct6=101111, funct3=101, opcode=1010111; the instruction is 32 bits.
Vector operands and results are SEW bits, EMUL=LMUL. Same-width source/destination overlap is legal; equal registers require equal initial bits. rs1 selects an FP f register. With FLEN>SEW a valid NaN box supplies the low SEW bits, while an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; sources cannot read v0 at both data EEW and mask EEW=1.
Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Negate the product. A separately rounded multiply followed by add/subtract, or negating a previously computed final sum, is not equivalent. Only active-element FP exceptions accrue in fflags; vxrm is not used.
V 1.0 applies to RV32/RV64, supports FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0.
The animation fixes VLEN=4096, LMUL=m1, vstart=0, frm=RNE, FLEN=64, and ta/ma. It calculates finite binary32/64 results, assuming valid NaN-boxing for VF at SEW=32. NaNs, infinities, overflow, and full fflags are outside this model. Teaching steps are not processor cycles.
Common Usage Scenarios
Negated-product fused operation
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Vector inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: old v1=[5,5,5,5], ft0=4, v2=[3,3,3,3] → v1=[-7,-7,-7,-7]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax is vd, rs1, vs2[, v0.t]; compute -(f[rs1] * vs2[i]) + old vd[i]. Old vd is the minuend. Read all three inputs before one fused dynamic-frm rounding. funct6=101111, funct3=101, opcode=1010111; the instruction is 32 bits.
- Vector operands and results are SEW bits, EMUL=LMUL. Same-width source/destination overlap is legal; equal registers require equal initial bits. rs1 selects an FP f register. With FLEN>SEW a valid NaN box supplies the low SEW bits, while an invalid box supplies canonical NaN; FLEN<SEW is reserved.
Semantic Check
- Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; sources cannot read v0 at both data EEW and mask EEW=1.
- Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- Negate the product. A separately rounded multiply followed by add/subtract, or negating a previously computed final sum, is not equivalent. Only active-element FP exceptions accrue in fflags; vxrm is not used.
- V 1.0 applies to RV32/RV64, supports FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0.
- The animation fixes VLEN=4096, LMUL=m1, vstart=0, frm=RNE, FLEN=64, and ta/ma. It calculates finite binary32/64 results, assuming valid NaN-boxing for VF at SEW=32. NaNs, infinities, overflow, and full fflags are outside this model. Teaching steps are not processor cycles.
Pitfalls / Common Confusions
Old vd is the minuend. Follow the formula when binding inputs; do not swap vs2 and old vd.
A separately rounded multiply and add/subtract is not fused. Negating the product or final sum can differ for signed zero.
ta/ma does not guarantee zeros; vl=0 or vstart≥vl updates no destination elements. Masked vd cannot overlap v0; equal registers require equal initial values.
FAQ
Does rounding use frm or vxrm?
A valid dynamic frm rounds the fused result once; vxrm does not control FP operations. Only active-element FP exceptions accrue in fflags.