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VFMSUB.VF

RISC-V VFMSUB.VF Instruction Details

Instruction ManualV-type

Floating-point fused multiply-add/subtract: vd[i] = +(f[rs1] * vd[i]) - vs2[i].

Instruction Syntax

vfmsub.vf vd, rs1, vs2, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VVector OperationsFloating-Point

Related Search Terms

VFMSUB.VF instruction RISC-V VFMSUB.VF vfmsub.vf syntax vfmsub.vf RVV FP FMA fused multiply add

Instruction Behavior

VFMSUB.VF follows the official RVV FMA formula: vd[i] = +(f[rs1] * vd[i]) - vs2[i]. The multiply and add/subtract are fused with one rounding and no intermediate rounded product; the old vd value is also a multiplicand, and vs2 is the subtrahend. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.

VFMSUB.VF Decode And Execute Animation

Decode the OP-V encoding and execute fused multiply-subtract lane by lane: each active lane multiplies f[rs1] and old vd[i], then subtracts vs2[i] with one rounding.

Instruction input

vfmsub.vf

vdUse v0-v31vs2Use v0-v31rs1FP register f0-f31/ABIvmexecution mask control

Execution context

VLSEW

LMULm1fixed register-group multiplier

VLEN4096fixed vector-register length (bits)

VLMAX128maximum element count at m1

vstart0prestart elements are outside this animation

frmRNEfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm

FP stateFS enabledFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled

vta/vmata, matail/inactive policy

opcode1010111OP-V major opcode

vd accumulatorComma-separated finite values, count must equal VL, representable as finite binary32vs2 elementsComma-separated finite values, count must equal VL, representable as finite binary32f[rs1]finite FP demo value, representable as finite binary32v0 mask bits0/1 string, length must equal VL

Encoding fields

0xa8855257

31..26

24..20

19..15

14..12

11..7

6..0

101010

funct6

01000

vs2

01010

rs1

101

funct3

00100

1010111

OP-V

Execution data path

lane 0: fma(1.5, 0.5, -1) -> -0.25

This lane follows the current-step highlight; the remaining lane results appear below.

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

fma(1.5, 0.5, -1)

-0.25

i=1active

fma(1.5, -1, -1.5)

-3

i=2skip

v0.t=0, not executed

i=3active

fma(1.5, -2.5, -2.5)

-6.25

i=4active

fma(1.5, 4, --3)

i=5active

fma(1.5, -4.5, -3.5)

-10.25

i=6skip

v0.t=0, not executed

i=7active

fma(1.5, -8.5, -4.5)

-17.25

In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, (vs1 * old vd) - vs2 is fused in each active lane and rounded only once to the current SEW. The animation explicitly reads old vd; finite inputs use exact binary intermediates so a pre-rounded product is not presented as architectural state. The real instruction uses dynamic frm; use of an invalid frm is reserved even when VL=0 or no elements are active. NaNs, infinities, and accrued fflags remain governed by the official RVV FP rules.

Quick Understanding & Search Notes

The key facts for VFMSUB.VF are the official FMA formula vd[i] = +(f[rs1] * vd[i]) - vs2[i] and single-rounding semantics.

The OPFVF encoding is funct6=101010, funct3=101, opcode=1010111; old vd is a multiplicand and rs1 selects the FP scalar f[rs1].

The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.

vm=0 uses v0 as the execution mask and vm=1 is unmasked.

Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, and fixed-point vxrm does not control these instructions.

Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFMSUB.VF, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vf: one vector source and one floating-point scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Polynomial Evaluation

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmsub.vf v1, ft0, v2 # vd[i] = +(f[rs1] * vd[i]) - vs2[i]».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is V-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Use the formula vd[i] = +(f[rs1] * vd[i]) - vs2[i]; do not swap the roles of vs2, vs1, f[rs1], or the old vd value.

This is fused operation, not a separately rounded multiply followed by add/subtract.

FAQ

Do these instructions use vxrm?

No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.