Do these instructions use vxrm?
No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFMSUB.VV
RISC-V VFMSUB.VV Instruction Details
Instruction ManualV-typeVFMSUB.VV computes vd[i] = (vs1[i] * old vd[i]) - vs2[i] on active elements, with a single rounding of the fused result.
Instruction Syntax
vfmsub.vv vd, vs1, vs2, vm
Operand Breakdown
Ternary assembly order is vd, vs1, vs2, vm. Old vd is the multiplicand and vs2 is the subtrahend. Same-width overlap is legal; equal registers read equal initial values.
vs1, vs2 and old vd are read at SEW; there is no scalar or immediate operand.
Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) compute; prestart is unchanged. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Otherwise inactive/tail values follow vma/vta; successful execution resets vstart=0.
Assembly vm is optional v0.t; omission means vm=1. Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. Only active-element exceptions accrue in fflags.
V supports FP32/FP64 and depends on F/D; FP16 arithmetic requires Zvfh. The animation fixes VLEN=4096, m1, vstart=0, valid NaN-boxing and finite RNE paths, without full fflags.
VVector OperationsFloating-Point
Instruction Behavior
VFMSUB.VV computes vd[i] = (vs1[i] * old vd[i]) - vs2[i] on active elements. Multiplication and subtraction are fused, with only the final result rounded by frm; old vd is the multiplicand and vs2 is the subtrahend. V provides FP32/FP64 with matching scalar F/D support. FP16 arithmetic additionally requires Zvfh; base V does not include it.
VFMSUB.VV Decode And Execute Animation
Decode the OP-V encoding and execute fused multiply-subtract lane by lane: each active lane multiplies vs1[i] and old vd[i], then subtracts vs2[i] with one rounding.
Instruction input
vfmsub.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xa8861257
31..26
25
24..20
19..15
14..12
11..7
6..0
101010
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma(0.5, 0.5, -(1)) -> -0.75
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma(0.5, 0.5, -(1))
-0.75
i=1active
fma(1, -1, -(1.5))
-2.5
i=2skip
v0.t=0, not executed
--
i=3active
fma(2, -2.5, -(2.5))
-7.5
i=4active
fma(2.5, 4, -(-3))
13
i=5active
fma(3, -4.5, -(3.5))
-17
i=6skip
v0.t=0, not executed
--
i=7active
fma(4, -8.5, -(4.5))
-38.5
In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, (vs1[i] * old vd[i]) - vs2[i] is fused in each active lane and rounded only once to the current SEW. The animation explicitly reads old vd; finite inputs use exact binary intermediates so a pre-rounded product is not presented as architectural state. The real instruction uses dynamic frm; use of an invalid frm is reserved even when VL=0 or no elements are active. NaNs, infinities, and accrued fflags remain governed by the official RVV FP rules.
Old vd is the multiplicand. Equal vector registers must have equal initial bits. VF scalars are read at FLEN=64, with valid NaN-boxing assumed for SEW=32; this animation computes finite RNE results without displaying fflags.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, and supported SEW. FP inputs are first represented as binary32/64. VL=0 updates no destination elements; same-width source/destination overlap is allowed. Inactive and tail values follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
vd[i] = (vs1[i] * old vd[i]) - vs2[i]; old vd is the multiplicand, and the fused result rounds once.
The OPFVV encoding is funct6=101010, funct3=001, opcode=1010111; old vd is multiplied with same-lane vs1, so the destination is not a pure output.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, and fixed-point vxrm does not control these instructions.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1). Prestart is unchanged; vl=0 or vstart≥vl leaves all destination elements, including tails, unchanged.
Assembly vm is optional v0.t; omission means vm=1. Masked vd cannot overlap v0; v0 cannot supply both EEW=1 mask and SEW data sources.
Require valid vtype, supported FP widths and matching scalar extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0. Only active-element exceptions accrue in fflags.
Vector Execution Context
Ternary assembly order is vd, vs1, vs2, vm. Old vd is the multiplicand and vs2 is the subtrahend. Same-width overlap is legal; equal registers read equal initial values.
vs1, vs2 and old vd are read at SEW; there is no scalar or immediate operand.
Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) compute; prestart is unchanged. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Otherwise inactive/tail values follow vma/vta; successful execution resets vstart=0.
Assembly vm is optional v0.t; omission means vm=1. Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. Only active-element exceptions accrue in fflags.
V supports FP32/FP64 and depends on F/D; FP16 arithmetic requires Zvfh. The animation fixes VLEN=4096, m1, vstart=0, valid NaN-boxing and finite RNE paths, without full fflags.
Common Usage Scenarios
Fused multiply-subtract
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4; the example is unmasked and VF scalars are validly NaN-boxed at FLEN=64. old v1=[1,2,-3,4], v2=[2,4,-2,0], v3=[3,-1,2,5] → v1=[-1,9,4,-5]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Ternary assembly order is vd, vs1, vs2, vm. Old vd is the multiplicand and vs2 is the subtrahend. Same-width overlap is legal; equal registers read equal initial values.
- vs1, vs2 and old vd are read at SEW; there is no scalar or immediate operand.
Semantic Check
- Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) compute; prestart is unchanged. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Otherwise inactive/tail values follow vma/vta; successful execution resets vstart=0.
- Assembly vm is optional v0.t; omission means vm=1. Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data.
- Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. Only active-element exceptions accrue in fflags.
- V supports FP32/FP64 and depends on F/D; FP16 arithmetic requires Zvfh. The animation fixes VLEN=4096, m1, vstart=0, valid NaN-boxing and finite RNE paths, without full fflags.
Pitfalls / Common Confusions
Use vd[i] = (vs1[i] * old vd[i]) - vs2[i]; old vd is the multiplicand and vs2 is the subtrahend.
This is fused operation, not a separately rounded multiply followed by add/subtract.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.