How does VFNCVT differ from VFWCVT?
VFNCVT narrows from 2*SEW source elements to SEW destination elements; VFWCVT widens from SEW source elements to 2*SEW destination elements. The direction, register-group size, and allowed overlap rules differ.
VFNCVT.RTZ.X.F.W
RISC-V VFNCVT.RTZ.X.F.W Instruction Details
Instruction ManualV-type (OP-V / OPFVV VFUNARY0)Narrow 2*SEW FP source elements to SEW signed integers with fixed round-toward-zero.
Instruction Syntax
vfncvt.rtz.x.f.w vd, vs2[, v0.t]
Operand Breakdown
Syntax is vd, vs2[, v0.t]; vs1=10111 is an encoding selector, not a second source. funct6=010010, funct3=001, opcode=1010111; the instruction is 32 bits.
Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. Groups are at most eight registers and align to their size. Narrowing overlap must start at the same lowest register and forces mask/tail agnostic.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0, and a source cannot read v0 both at data EEW and mask EEW=1.
Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; successful execution resets vstart=0.
Result rounding is fixed toward zero. Out-of-range conversions clip by scalar conversion rules and set NV; valid inexact conversions set NX. This animation accepts only finite values whose rounded result fits the 32-bit destination.
V supports this 64-to-32 path on RV32/RV64; this instruction at SEW=16 requires Zvfh. The teaching context fixes valid vtype, enabled VS/FS, and valid frm. Invalid frm use is reserved, even for fixed rounding or vl=0. Only active-element exceptions accrue in fflags; full fflags are outside the animation.
VVector Type ConvertFloating-Point
Instruction Behavior
VFNCVT.RTZ.X.F.W reads 2*SEW FP source elements, uses instruction-specified fixed round-toward-zero to produce SEW signed integers, and writes vd. Result rounding is not selected by frm; frm validity still follows the official vector FP rules.
VFNCVT.RTZ.X.F.W Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 narrowing conversion lane by lane: each active lane converts the 2*SEW FP value in vs2[i] to a signed integer.
Instruction input
vfncvt.rtz.x.f.w
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
source EEWsource element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
vs1VFUNARY0 conversion selector
Encoding fields
0x488b9257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
10111
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: narrow_trunc_signed(-3.75) -> -3
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
narrow_trunc_signed(-3.75)
-3
i=1active
narrow_trunc_signed(-2.5)
-2
i=2skip
v0.t=0, not executed
--
i=3active
narrow_trunc_signed(-0.25)
0
i=4active
narrow_trunc_signed(0.25)
0
i=5active
narrow_trunc_signed(1.5)
1
i=6skip
v0.t=0, not executed
--
i=7active
narrow_trunc_signed(3.75)
3
source EEW=64 / binary64 -> destination width=32 demo values cover finite FP inputs whose rounded integer result fits this demo's integer range. The RTZ form fixes result rounding toward zero, but frm must still be valid. Selecting reserved frm rejects encoding and execution. NaN, infinity, out-of-range cases, and fflags still follow the official RVV/scalar FP conversion rules; the 64-bit integer demo range avoids JavaScript unsafe-integer edges.
The teaching context fixes VLEN=4096, LMUL=m1, SEW=32, vstart=0, valid vtype, enabled VS/FS, and valid frm. The source is an even vs2..vs2+1 group and the destination is one register; overlap must start at the source group's lowest register and forces mask/tail agnostic. VL=0 updates no destination elements, including tails. Inactive and tail values remain unspecified in this display; full fflags are not modeled. NaNs, infinities, and out-of-range integer conversions are legal FP inputs outside this model, not illegal instructions.
Quick Understanding & Search Notes
When you see `rtz`, first note fixed round-toward-zero, then read `.w` as narrowing from 2*SEW source to SEW destination.
VFNCVT.RTZ.X.F.W uses the RVV VFUNARY0 conversion encoding space: selector(vs1[19:15])=10111, funct6=010010, funct3=001 (OPFVV), and opcode=1010111 (OP-V). This vs1 field is an encoding selector, not a source register in the assembly syntax.
This family is narrowing: the vs2 source elements are 2*SEW wide and the vd destination elements are SEW wide; it is not single-width VFCVT or widening VFWCVT.
The narrowing source register group has twice the destination EMUL; by the official narrowing overlap rule, if the destination group overlaps the source group, the destination group's lowest-numbered register must equal the source group's lowest-numbered register.
Only active elements within vl execute; with vm=0, v0.t controls activity, and inactive/tail elements follow the current vma/vta policy. At vl=0 or vstart≥vl no destination elements change, including tails; legal source/destination overlap with different EEWs forces mask/tail agnostic.
Ordinary FP conversions use frm; rtz/rod forms have instruction-specified result rounding, while frm validity still follows the official vector FP rules; these conversions do not use fixed-point vxrm.
V supports this SEW=32, 64-to-32 conversion on RV32/RV64. Groups cannot exceed eight registers and multi-register groups align to their size. Valid vtype, enabled VS/FS, and valid frm are required; invalid frm use is reserved even at vl=0. Only active-element exceptions accrue in fflags.
The animation demonstrates only the finite 64-to-32 path; NaNs, infinities, out-of-range cases, and full fflags are outside the animation. This instruction at SEW=16 requires Zvfh.
Vector Execution Context
Syntax is vd, vs2[, v0.t]; vs1=10111 is an encoding selector, not a second source. funct6=010010, funct3=001, opcode=1010111; the instruction is 32 bits.
Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. Groups are at most eight registers and align to their size. Narrowing overlap must start at the same lowest register and forces mask/tail agnostic.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0, and a source cannot read v0 both at data EEW and mask EEW=1.
Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; successful execution resets vstart=0.
Result rounding is fixed toward zero. Out-of-range conversions clip by scalar conversion rules and set NV; valid inexact conversions set NX. This animation accepts only finite values whose rounded result fits the 32-bit destination.
V supports this 64-to-32 path on RV32/RV64; this instruction at SEW=16 requires Zvfh. The teaching context fixes valid vtype, enabled VS/FS, and valid frm. Invalid frm use is reserved, even for fixed rounding or vl=0. Only active-element exceptions accrue in fflags; full fflags are outside the animation.
Common Usage Scenarios
Truncate wide FP to narrower signed integers
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; vsetvli sets vl=4 and vstart=0. The source group is v2/v3; omitting v0.t makes the example unmasked: binary64 v2=[-3.75,-0.25,1.5,2.5] → int32 v1=[-3,0,1,2] (NX). Inexact conversions accrue NX; tails follow ta without assumed zeroing.
Vectorized format conversion
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; vsetvli sets vl=4 and vstart=0. The source group is v2/v3; omitting v0.t makes the example unmasked: binary64 v2=[-3.75,-0.25,1.5,2.5] → int32 v1=[-3,0,1,2] (NX). Inexact conversions accrue NX; tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax is vd, vs2[, v0.t]; vs1=10111 is an encoding selector, not a second source. funct6=010010, funct3=001, opcode=1010111; the instruction is 32 bits.
- Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. Groups are at most eight registers and align to their size. Narrowing overlap must start at the same lowest register and forces mask/tail agnostic.
Semantic Check
- Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0, and a source cannot read v0 both at data EEW and mask EEW=1.
- Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; successful execution resets vstart=0.
- Result rounding is fixed toward zero. Out-of-range conversions clip by scalar conversion rules and set NV; valid inexact conversions set NX. This animation accepts only finite values whose rounded result fits the 32-bit destination.
- V supports this 64-to-32 path on RV32/RV64; this instruction at SEW=16 requires Zvfh. The teaching context fixes valid vtype, enabled VS/FS, and valid frm. Invalid frm use is reserved, even for fixed rounding or vl=0. Only active-element exceptions accrue in fflags; full fflags are outside the animation.
Pitfalls / Common Confusions
This form fixes result rounding to round-toward-zero and differs from dynamic frm forms; frm validity still follows the official vector FP rules.
The source register group is interpreted as 2*SEW elements, not destination-SEW elements.
FAQ
Does VFNCVT use vxrm for rounding?
No. VFNCVT is a floating-point/integer conversion family: ordinary forms use floating-point frm, while rtz and rod are instruction-specified fixed rounding forms. vxrm is for fixed-point rounding instructions.