Is VFCVT.RTZ.X.F.V a widening or narrowing conversion?
No. This VFCVT.RTZ.X.F.V form is a single-width VFCVT conversion: input and output both use the current SEW. Widening uses VFWCVT, and narrowing uses VFNCVT.
VFCVT.RTZ.X.F.V
RISC-V VFCVT.RTZ.X.F.V Instruction Details
Instruction ManualOPFVVVFCVT.RTZ.X.F.V performs an RVV single-width FP-to-signed-integer conversion for each active element and writes the result to vd[i].
Instruction Syntax
vfcvt.rtz.x.f.v vd, vs2, vm
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.
Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.
Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.
Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.
Result rounding is fixed toward zero. A rounded value outside the signed destination range is clipped and sets NV; +infinity/NaN yields the signed maximum, and -infinity yields the minimum. A changed value sets NX if NV is not set. The animation accepts only finite inputs whose rounded result fits its demo range.
VVector Type ConvertFloating-Point
Instruction Behavior
VFCVT.RTZ.X.F.V is a RISC-V V-extension single-width floating-point/integer conversion instruction with syntax vfcvt.rtz.x.f.v vd, vs2, vm. For active elements within vl, it reads vs2[i], performs a same-SEW FP-to-signed-integer conversion, and writes the result to vd[i]; vm=0 uses v0.t as the execution mask and vm=1 is unmasked. The encoding uses OP-V, funct6=010010, funct3=001, and vs1 selector 00111; rounding is fixed toward zero rather than selected by frm, but frm must still be valid.
VFCVT.RTZ.X.F.V Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 single-width conversion lane by lane: each active lane converts the FP value in vs2[i] to a signed integer.
Instruction input
vfcvt.rtz.x.f.v
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
vs1VFUNARY0 conversion selector
Encoding fields
0x48839257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
00111
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: trunc_signed(-3.75) -> -3
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
trunc_signed(-3.75)
-3
i=1active
trunc_signed(-2.5)
-2
i=2skip
v0.t=0, not executed
--
i=3active
trunc_signed(-0.25)
0
i=4active
trunc_signed(0.25)
0
i=5active
trunc_signed(1.5)
1
i=6skip
v0.t=0, not executed
--
i=7active
trunc_signed(3.75)
3
SEW=32 / binary32 demo values cover finite FP inputs whose rounded integer result fits this demo's integer range. The RTZ form fixes result rounding toward zero, but frm must still be valid. Selecting reserved frm rejects encoding and execution. NaN, infinity, out-of-range cases, and fflags still follow the official RVV/scalar FP conversion rules; the 64-bit integer demo range avoids JavaScript unsafe-integer edges.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, and supported SEW. FP inputs are first represented as binary32/64. VL=0 updates no destination elements; same-width source/destination overlap is allowed. Inactive and tail values follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
VFCVT.RTZ.X.F.V is best understood as a VFUNARY0 single-width conversion: after decoding vs1=00111, active elements convert vs2[i] from FP to a signed integer.
In the OP-V encoding, funct6=010010 and funct3=001 select the vector FP/integer conversion group, and vs1=00111 selects VFCVT.RTZ.X.F.V.
The syntax input contains only vd, vs2, and vm; VL, SEW, frm, v0.t, and element values are execution context.
This is a single-width conversion, so input and output both use the current SEW.
This RTZ form always rounds toward zero rather than selecting its rounding direction from frm, but frm must still be valid.
Only active elements within vl execute; vm=0 uses v0.t and vm=1 is unmasked.
NaNs, infinities, out-of-range cases, and inexact/invalid flags follow the official RVV and scalar FP conversion rules.
This animation demonstrates SEW=32/64. These single-width conversions at SEW=16 require Zvfh; Zvfhmin alone adds only FP widening/narrowing conversions between binary16 and binary32.
Vector Execution Context
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.
Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.
Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.
Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.
Result rounding is fixed toward zero. A rounded value outside the signed destination range is clipped and sets NV; +infinity/NaN yields the signed maximum, and -infinity yields the minimum. A changed value sets NX if NV is not set. The animation accepts only finite inputs whose rounded result fits its demo range.
Common Usage Scenarios
FP results to integer vectors
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[-3.75,-0.25,1.5,3.75] → v1=[-3,0,1,3] (NX). Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.
Truncating numeric conversion
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[-3.75,-0.25,1.5,3.75] → v1=[-3,0,1,3] (NX). Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.
Mixed-type vector math
Assume V/VS/FS enabled, frm=RNE, vstart=0, supported e32,m1, VLMAX≥4 and a0=4. The example is unmasked, so all four body elements execute. Initial values and results: v2=[-3.75,-0.25,1.5,3.75] → v1=[-3,0,1,3] (NX). Conversion results use the destination integer/FP type; tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed. VFADD.VV also reads a SEW-wide vs1 vector, and equal source registers read equal initial values. Unary instructions use the encoded vs1 bits as a fixed selector.
- Require V, enabled VS/FS and supported vtype. V supports binary32/64; these instructions at SEW=16 require Zvfh, not Zvfhmin alone. FS=Off raises illegal instruction; with H and V=1, vsstatus.FS/VS must also be enabled.
Semantic Check
- Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); omitting v0.t means vm=1. Prestart elements are unchanged, and inactive/tail elements follow vma/vta. VL=0 or vstart≥vl leaves the entire destination unchanged; successful completion resets vstart=0. Implementations may reject nonzero vstart values they cannot produce.
- Masked vd cannot overlap v0; v0 cannot supply both an EEW=1 mask and SEW data source. Invalid frm use is reserved even without rounding, at VL=0 or vstart≥vl; an illegal-instruction exception is not guaranteed by that rule.
- Result rounding is fixed toward zero. A rounded value outside the signed destination range is clipped and sets NV; +infinity/NaN yields the signed maximum, and -infinity yields the minimum. A changed value sets NX if NV is not set. The animation accepts only finite inputs whose rounded result fits its demo range.
Pitfalls / Common Confusions
This is a single-width conversion: input and output both use the current SEW; do not treat it as a VFWCVT widening or VFNCVT narrowing form.
The RTZ form always rounds toward zero rather than selecting its rounding direction from frm; all vector FP instructions still require a valid frm value.
VFCVT.RTZ.X.F.V interprets source elements as FP values before converting them to signed integers; it is not FCLASS classification or a bit-pattern move.
With vm=0, v0.t selects active elements only; masked-off elements do not produce the conversion result shown by the animation.
NaNs, infinities, out-of-range values, and FP exception flags follow the official FP conversion rules; the page animation demonstrates only finite, checkable in-range examples.
Do not read the SEW=32/64 animation examples as a complete SEW=16 half-precision simulator; these SEW=16 single-width conversions require Zvfh; Zvfhmin alone adds only FP widening/narrowing conversions between binary16 and binary32.
FAQ
Where does VFCVT.RTZ.X.F.V take its rounding mode from?
The RTZ form always rounds toward zero rather than selecting its rounding direction from frm, but frm must still be valid.
How does VFCVT.RTZ.X.F.V use the mask operand?
With vm=0, only active elements selected by v0.t are converted; vm=1 is unmasked. Inactive and tail elements follow the current vma/vta policies.