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VFCVT.F.X.V

RISC-V VFCVT.F.X.V Instruction Details

Instruction ManualR-type

VFCVT.F.X.V performs an RVV single-width signed-integer-to-FP conversion for each active element and writes the result to vd[i].

Instruction Syntax

vfcvt.f.x.v vd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector Type ConvertFloating-Point
Related Search Terms
VFCVT.F.X.V instructionRISC-V VFCVT.F.X.Vvfcvt.f.x.v syntaxvfcvt.f.x.v encodingRVV single-width convertsigned int to FPVFCVT frm roundingvfcvt.f.x.v v0.t

Instruction Behavior

VFCVT.F.X.V is a RISC-V V-extension single-width floating-point/integer conversion instruction with syntax vfcvt.f.x.v vd, vs2, vm. For active elements within vl, it reads vs2[i], performs a same-SEW signed-integer-to-FP conversion, and writes the result to vd[i]; vm=0 uses v0.t as the execution mask and vm=1 is unmasked. The encoding uses OP-V, funct6=010010, funct3=001, and vs1 selector 00011; it uses dynamic frm when rounding is required.

VFCVT.F.X.V Decode And Execute Animation

Decode the OP-V encoding and execute a VFUNARY0 single-width conversion lane by lane: each active lane converts the signed integer in vs2[i] to a same-SEW FP value.

Step 1 / 15
Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Instruction input
vfcvt.f.x.v
Execution context
frm
RNE
demo dynamic rounding mode
vta/vma
ta, ma
tail/inactive policy
opcode
1010111
OP-V major opcode
vs1
00011
VFUNARY0 conversion selector
Encoding fields
0x48819257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
00011
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
int_to_float(-8)
-8
i=1active
int_to_float(-3)
-3
i=2skip
v0.t=0, not executed
--
i=3active
int_to_float(0)
0
i=4active
int_to_float(1)
1
i=5active
int_to_float(3)
3
i=6skip
v0.t=0, not executed
--
i=7active
int_to_float(15)
15
SEW=32 / binary32 demo values convert signed integer elements to same-SEW FP results; dynamic frm is used when rounding is required, and this animation shows RNE. To avoid JavaScript precision ambiguity, editable inputs are limited to small checkable integer samples.

Quick Understanding & Search Notes

VFCVT.F.X.V is best understood as a VFUNARY0 single-width conversion: after decoding vs1=00011, active elements convert vs2[i] from a signed integer to FP.

In the OP-V encoding, funct6=010010 and funct3=001 select the vector FP/integer conversion group, and vs1=00011 selects VFCVT.F.X.V.
The syntax input contains only vd, vs2, and vm; VL, SEW, frm, v0.t, and element values are execution context.
This is a single-width conversion, so input and output both use the current SEW.
When rounding is required, the floating-point dynamic rounding mode frm is used.
Only active elements within vl execute; vm=0 uses v0.t and vm=1 is unmasked.
Integer-to-FP conversions can round according to frm and set inexact when the FP result differs from the integer value; they do not have NaN or infinity source operands.
This page animation currently demonstrates the SEW=32/64 binary32/binary64 paths; SEW=16 half-precision behavior is governed by the official vector half-precision support rules such as Zvfh/Zvfhmin.
RISC-V Unprivileged ISA Manual: V extension vector FP/integer conversion instructionsRISC-V Unprivileged ISA Manual: scalar FP conversion and rounding rules

Vector Execution Context

When reading VFCVT.F.X.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Integer data to FP vectors

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfcvt.f.x.v v1, v2».

Mixed-type vector math

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfcvt.f.x.v v1, v2».

Vectorized numeric preparation

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfcvt.f.x.v v1, v2».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is a single-width conversion: input and output both use the current SEW; do not treat it as a VFWCVT widening or VFNCVT narrowing form.
When rounding is required, it uses floating-point frm; do not confuse this with the fixed-point rounding mode vxrm.
VFCVT.F.X.V interprets source elements as signed integers before converting them to FP; it is not an FP bit-pattern move.
With vm=0, v0.t selects active elements only; masked-off elements do not produce the conversion result shown by the animation.
Integer-to-FP conversion has no NaN or infinity source operand; inexact results and rounding behavior follow the official FP conversion rules, while the page animation demonstrates small, checkable integer examples.
Do not read the SEW=32/64 animation examples as a complete SEW=16 half-precision simulator; half-precision conversion still follows the official Zvfh/Zvfhmin-related rules.

FAQ

Is VFCVT.F.X.V a widening or narrowing conversion?

No. This VFCVT.F.X.V form is a single-width VFCVT conversion: input and output both use the current SEW. Widening uses VFWCVT, and narrowing uses VFNCVT.

Where does VFCVT.F.X.V take its rounding mode from?

When rounding is required, it uses the floating-point dynamic rounding mode frm, not the fixed-point vxrm.

How does VFCVT.F.X.V use the mask operand?

With vm=0, only active elements selected by v0.t are converted; vm=1 is unmasked. Inactive and tail elements follow the current vma/vta policies.