Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFNCVT.F.X.W
RISC-V VFNCVT.F.X.W Instruction Details
Instruction ManualR-typeNarrow 2*SEW signed-integer source elements to SEW FP results.
Instruction Syntax
vfncvt.f.x.w vd, vs2, vm
Operand Breakdown
vd: narrowing destination vector register group, with elements at the current SEW.
vs2: the only source vector register group, with source elements at 2*SEW; the assembly syntax has no vs1 source operand.
vs1[19:15]: the VFUNARY0 selector field in the encoding, used to distinguish the specific vfncvt.*.w conversion; it is not a source register.
vm: vm=0 uses v0.t as the execution mask and vm=1 is unmasked.
VVector Type ConvertFloating-Point
Instruction Behavior
VFNCVT.F.X.W reads 2*SEW signed-integer elements from vs2, converts them to SEW FP results, and writes vd. If the destination FP format cannot exactly represent the source integer, rounding is controlled by frm.
VFNCVT.F.X.W Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 narrowing conversion lane by lane: each active lane converts the 2*SEW signed integer in vs2[i] to a SEW FP value.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Instruction input
vfncvt.f.x.w
Execution context
frm
RNE
demo dynamic rounding modesource EEW
64
source element widthvta/vma
ta, ma
tail/inactive policyopcode
1010111
OP-V major opcodevs1
10011
VFUNARY0 conversion selectorEncoding fields
0x48899257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
10011
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
narrow_int_to_float(-8)
-8
i=1active
narrow_int_to_float(-3)
-3
i=2skip
v0.t=0, not executed
--
i=3active
narrow_int_to_float(0)
0
i=4active
narrow_int_to_float(1)
1
i=5active
narrow_int_to_float(3)
3
i=6skip
v0.t=0, not executed
--
i=7active
narrow_int_to_float(15)
15
source EEW=64 integer -> destination binary32 demo values convert signed integer elements to SEW FP results; dynamic frm is used when rounding is required, and this animation shows RNE. To avoid JavaScript precision ambiguity, editable inputs are limited to small checkable integer samples.
Quick Understanding & Search Notes
This is a 2*SEW signed-integer to SEW FP narrowing conversion.
VFNCVT.F.X.W uses the RVV VFUNARY0 conversion encoding space: selector(vs1[19:15])=10011, funct6=010010, funct3=001 (OPFVV), and opcode=1010111 (OP-V). This vs1 field is an encoding selector, not a source register in the assembly syntax.
This family is narrowing: the vs2 source elements are 2*SEW wide and the vd destination elements are SEW wide; it is not single-width VFCVT or widening VFWCVT.
The narrowing source register group has twice the destination EMUL; by the official narrowing overlap rule, if the destination group overlaps the source group, the destination group's lowest-numbered register must equal the source group's lowest-numbered register.
Only active elements within vl execute; with vm=0, v0.t controls activity, and inactive/tail elements follow the current vma/vta policy.
Ordinary FP conversions use frm; rtz/rod forms have instruction-specified result rounding, while frm validity still follows the official vector FP rules; these conversions do not use fixed-point vxrm.
Vector Execution Context
When reading VFNCVT.F.X.W, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Compress wide signed integers into narrower FP format
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfncvt.f.x.w v1, v2».
Mixed integer/FP vector processing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfncvt.f.x.w v1, v2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
`x` means the integer source is interpreted as signed.
The narrowing source group is 2*SEW; if the vd destination group overlaps the source group, the destination group's lowest-numbered register must equal the source group's lowest-numbered register.
FAQ
How does VFNCVT differ from VFWCVT?
VFNCVT narrows from 2*SEW source elements to SEW destination elements; VFWCVT widens from SEW source elements to 2*SEW destination elements. The direction, register-group size, and allowed overlap rules differ.
Does VFNCVT use vxrm for rounding?
No. VFNCVT is a floating-point/integer conversion family: ordinary forms use floating-point frm, while rtz and rod are instruction-specified fixed rounding forms. vxrm is for fixed-point rounding instructions.