How does VFNCVT differ from VFWCVT?
VFNCVT narrows from 2*SEW source elements to SEW destination elements; VFWCVT widens from SEW source elements to 2*SEW destination elements. The direction, register-group size, and allowed overlap rules differ.
VFNCVT.F.F.W
RISC-V VFNCVT.F.F.W Instruction Details
Instruction ManualV-type (OP-V / OPFVV VFUNARY0)Narrow 2*SEW FP source elements to SEW FP results using frm rounding.
Instruction Syntax
vfncvt.f.f.w vd, vs2, vm
Operand Breakdown
Syntax is vd, vs2, vm. Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. vs1=10100 is the VFUNARY0 selector, not a source register.
funct6=010010, funct3=001, opcode=1010111. Groups cannot exceed eight registers; multi-register groups must align to their size. Overlap must start at the same lowest register and forces mask/tail agnostic; Zvfhmin defines this conversion at SEW=16.
vm is optional v0.t; omission means vm=1. Only elements with vstart≤i<vl and an enabled mask compute. Masked vd cannot overlap v0, and a data source cannot also read the v0 mask with another EEW.
At vl=0 or vstart≥vl no destination elements, including tails, change; prestart is unchanged. Other inactive/tail values follow vma/vta, subject to the different-EEW overlap exception above. Successful execution resets vstart=0.
Ordinary narrowing uses dynamic frm, rather than fixed round-to-odd. Only active-element exceptions accrue in fflags. The animation shows finite binary64 to binary32 narrowing under RNE without NaNs, infinities, overflow, or full fflags.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
VVector Type ConvertFloating-Point
Instruction Behavior
VFNCVT.F.F.W converts 2*SEW-wide FP elements in vs2 into SEW-wide FP results in vd. It is the ordinary FP narrowing form using dynamic frm, not the round-to-odd variant. The source register group has EEW=2*SEW and EMUL=2*LMUL; no group may exceed eight registers. Legal source/destination overlap with different EEWs forces both mask and tail agnostic treatment. If it overlaps the destination group, their lowest-numbered registers must be the same or the encoding is reserved. At SEW=16, this instruction is defined only when Zvfhmin is implemented.
VFNCVT.F.F.W Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 narrowing conversion lane by lane: each active lane converts the 2*SEW FP value in vs2[i] to a SEW FP value.
Instruction input
vfncvt.f.f.w
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
source EEWsource element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
vs1VFUNARY0 conversion selector
Encoding fields
0x488a1257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
10100
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: narrow_float.frm(1.5) -> 1.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
narrow_float.frm(1.5)
1.5
i=1active
narrow_float.frm(-2.25)
-2.25
i=2skip
v0.t=0, not executed
--
i=3active
narrow_float.frm(-4.5)
-4.5
i=4active
narrow_float.frm(7.125)
7.125
i=5active
narrow_float.frm(-8.5)
-8.5
i=6skip
v0.t=0, not executed
--
i=7active
narrow_float.frm(-31.75)
-31.75
source EEW=64 / binary64 -> destination binary32: finite inputs narrow using dynamic frm; this model fixes RNE. NaNs, infinities, overflow, and fflags are outside the model; SEW=16 conversion requires Zvfhmin.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, enabled VS/FS, frm=RNE, and supported FP widths. VL=0 updates no destination elements, including tails. This page demonstrates binary64 to binary32 only. The source is an even vs2..vs2+1 group and the destination is one register. Overlap may begin at the source group’s lowest register; legal overlap with different EEWs forces mask/tail agnostic. Zvfhmin defines SEW=16 conversion, outside this animation. Inactive and tail elements follow ma/ta without definite displayed values.
Quick Understanding & Search Notes
This is a dynamic-frm 2*SEW FP to SEW FP narrowing conversion.
VFNCVT.F.F.W uses the RVV VFUNARY0 conversion encoding space: selector(vs1[19:15])=10100, funct6=010010, funct3=001 (OPFVV), and opcode=1010111 (OP-V). This vs1 field is an encoding selector, not a source register in the assembly syntax.
This family is narrowing: the vs2 source elements are 2*SEW wide and the vd destination elements are SEW wide; it is not single-width VFCVT or widening VFWCVT.
The narrowing source register group has twice the destination EMUL; by the official narrowing overlap rule, if the destination group overlaps the source group, the destination group's lowest-numbered register must equal the source group's lowest-numbered register.
Only active elements within vl execute; with vm=0, v0.t controls activity, and inactive/tail elements follow the current vma/vta policy, except legal source/destination overlap with different EEWs forces mask/tail agnostic.
VFNCVT.F.F.W uses dynamic frm; rtz/rod are fixed-rounding forms of other instructions. It does not use fixed-point vxrm, and at SEW=16 it is defined only with Zvfhmin.
Vector Execution Context
Syntax is vd, vs2, vm. Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. vs1=10100 is the VFUNARY0 selector, not a source register.
funct6=010010, funct3=001, opcode=1010111. Groups cannot exceed eight registers; multi-register groups must align to their size. Overlap must start at the same lowest register and forces mask/tail agnostic; Zvfhmin defines this conversion at SEW=16.
vm is optional v0.t; omission means vm=1. Only elements with vstart≤i<vl and an enabled mask compute. Masked vd cannot overlap v0, and a data source cannot also read the v0 mask with another EEW.
At vl=0 or vstart≥vl no destination elements, including tails, change; prestart is unchanged. Other inactive/tail values follow vma/vta, subject to the different-EEW overlap exception above. Successful execution resets vstart=0.
Ordinary narrowing uses dynamic frm, rather than fixed round-to-odd. Only active-element exceptions accrue in fflags. The animation shows finite binary64 to binary32 narrowing under RNE without NaNs, infinities, overflow, or full fflags.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Common Usage Scenarios
Compress after higher-precision FP computation
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. The wide source group starts at even v2 and occupies v2/v3. The example is unmasked: binary64 v2=[1.5,-2.25,3.75,-4.5] → binary32 v1=[1.5,-2.25,3.75,-4.5]. Elements after vl are tail; ta does not guarantee zeros.
Narrow FP vectors before storage
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. The wide source group starts at even v2 and occupies v2/v3. The example is unmasked: binary64 v2=[1.5,-2.25,3.75,-4.5] → binary32 v1=[1.5,-2.25,3.75,-4.5]. Elements after vl are tail; ta does not guarantee zeros.
Pre-Use Checklist
Syntax Check
- Syntax is vd, vs2, vm. Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. vs1=10100 is the VFUNARY0 selector, not a source register.
- funct6=010010, funct3=001, opcode=1010111. Groups cannot exceed eight registers; multi-register groups must align to their size. Overlap must start at the same lowest register and forces mask/tail agnostic; Zvfhmin defines this conversion at SEW=16.
Semantic Check
- vm is optional v0.t; omission means vm=1. Only elements with vstart≤i<vl and an enabled mask compute. Masked vd cannot overlap v0, and a data source cannot also read the v0 mask with another EEW.
- At vl=0 or vstart≥vl no destination elements, including tails, change; prestart is unchanged. Other inactive/tail values follow vma/vta, subject to the different-EEW overlap exception above. Successful execution resets vstart=0.
- Ordinary narrowing uses dynamic frm, rather than fixed round-to-odd. Only active-element exceptions accrue in fflags. The animation shows finite binary64 to binary32 narrowing under RNE without NaNs, infinities, overflow, or full fflags.
- Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Pitfalls / Common Confusions
This form uses frm and is not fixed round-to-odd; use vfncvt.rod.f.f.w when ROD is required.
At SEW=16 this instruction is defined only with Zvfhmin; when it overlaps the wide source group, vd must start at the same lowest-numbered register as vs2.
FAQ
Does VFNCVT use vxrm for rounding?
No. VFNCVT is a floating-point/integer conversion family: ordinary forms use floating-point frm, while rtz and rod are instruction-specified fixed rounding forms. vxrm is for fixed-point rounding instructions.