VFNCVT.F.F.W

RISC-V VFNCVT.F.F.W Instruction Details

Instruction ManualR-type

Narrow 2*SEW FP source elements to SEW FP results using frm rounding.

Instruction Syntax

vfncvt.f.f.w vd, vs2, vm

Operand Breakdown

vd: narrowing destination vector register group, with elements at the current SEW.

vs2: the only source vector register group, with source elements at 2*SEW; the assembly syntax has no vs1 source operand.

vs1[19:15]: the VFUNARY0 selector field in the encoding, used to distinguish the specific vfncvt.*.w conversion; it is not a source register.

vm: vm=0 uses v0.t as the execution mask and vm=1 is unmasked.

VZvfhminZvfhVector Type ConvertFloating-Point

Related Search Terms

vfncvt.f.f.w instruction RISC-V VFNCVT vfncvt.f.f.w encoding RVV FP narrowing float to float convert frm rounding

Instruction Behavior

VFNCVT.F.F.W reads 2*SEW FP elements from vs2, rounds them according to frm into SEW FP results, and writes vd. It lands a wider FP format into a narrower FP format, opposite in direction to VFWCVT.F.F.V.

VFNCVT.F.F.W Decode And Execute Animation

Decode the OP-V encoding and execute a VFUNARY0 narrowing conversion lane by lane: each active lane converts the 2*SEW FP value in vs2[i] to a SEW FP value.

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Instruction input

vfncvt.f.f.w

vdUse v0-v31vs2Use v0-v31vmexecution mask control

Execution context

VLSEW

frm

RNE

demo dynamic rounding mode

source EEW

source element width

vta/vma

ta, ma

tail/inactive policy

opcode

1010111

OP-V major opcode

vs2 elementsComma-separated finite values, count must equal VL

vs1

10100

VFUNARY0 conversion selector

v0 mask bits0/1 string, length must equal VL

Encoding fields

0x488a1257

31..26

24..20

19..15

14..12

11..7

6..0

010010

funct6

01000

vs2

10100

vs1/sel

001

funct3

00100

1010111

OP-V

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

narrow_float.frm(1.5)

1.5

i=1active

narrow_float.frm(-2.25)

-2.25

i=2skip

v0.t=0, not executed

i=3active

narrow_float.frm(-4.5)

-4.5

i=4active

narrow_float.frm(7.125)

7.125

i=5active

narrow_float.frm(-8.5)

-8.5

i=6skip

v0.t=0, not executed

i=7active

narrow_float.frm(-31.75)

-31.75

source EEW=64 / binary64 -> destination binary32 demo values show a 2*SEW FP value narrowed to a SEW FP value; this page uses dynamic frm, with RNE as a checkable demo mode. SEW=16/Zvfh and exception flags remain governed by the official manual.

Quick Understanding & Search Notes

This is a dynamic-frm 2*SEW FP to SEW FP narrowing conversion.

VFNCVT.F.F.W uses the RVV VFUNARY0 conversion encoding space: selector(vs1[19:15])=10100, funct6=010010, funct3=001 (OPFVV), and opcode=1010111 (OP-V). This vs1 field is an encoding selector, not a source register in the assembly syntax.

This family is narrowing: the vs2 source elements are 2*SEW wide and the vd destination elements are SEW wide; it is not single-width VFCVT or widening VFWCVT.

The narrowing source register group has twice the destination EMUL; by the official narrowing overlap rule, if the destination group overlaps the source group, the destination group's lowest-numbered register must equal the source group's lowest-numbered register.

Only active elements within vl execute; with vm=0, v0.t controls activity, and inactive/tail elements follow the current vma/vta policy.

Ordinary FP conversions use frm; rtz/rod forms have instruction-specified result rounding, while frm validity still follows the official vector FP rules; these conversions do not use fixed-point vxrm.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations RISC-V Unprivileged ISA Manual: F Standard Extension for Single-Precision Floating-Point

Vector Execution Context

When reading VFNCVT.F.F.W, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Compress after higher-precision FP computation

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfncvt.f.f.w v1, v2 # v1[i]=float(v2[i]), 64b→32b».

Narrow FP vectors before storage

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfncvt.f.f.w v1, v2 # v1[i]=float(v2[i]), 64b→32b».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This form uses frm and is not fixed round-to-odd; use vfncvt.rod.f.f.w when ROD is required.

SEW=16/Zvfh cases remain governed by the official half-precision rules.

FAQ

How does VFNCVT differ from VFWCVT?

VFNCVT narrows from 2*SEW source elements to SEW destination elements; VFWCVT widens from SEW source elements to 2*SEW destination elements. The direction, register-group size, and allowed overlap rules differ.

Does VFNCVT use vxrm for rounding?

No. VFNCVT is a floating-point/integer conversion family: ordinary forms use floating-point frm, while rtz and rod are instruction-specified fixed rounding forms. vxrm is for fixed-point rounding instructions.