How is VFWCVT.F.F.V different from VFCVT?
VFWCVT.F.F.V is a VFWCVT widening form: the source is SEW and the destination is 2*SEW. Single-width VFCVT uses the current SEW for both source and destination.
VFWCVT.F.F.V
RISC-V VFWCVT.F.F.V Instruction Details
Instruction ManualOPFVVVFWCVT.F.F.V widens each active vs2[i] from an SEW-wide FP value to a 2*SEW-wide FP result and writes vd[i].
Instruction Syntax
vfwcvt.f.f.v vd, vs2, vm
Operand Breakdown
Syntax: vfwcvt.f.f.v vd, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=010010. vs1=01100 is a VFUNARY0 selector, not a second vector source.
vs2 has EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved, while EMUL≤1 does not require even register numbers.
Single-width finite FP values widen exactly to the double-width IEEE FP format; NaNs follow scalar FP rules without guaranteed payload preservation. Every vector FP instruction still requires valid frm, including at vl=0; invalid frm use is reserved. vxrm is not used.
Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. A masked destination cannot include v0; one register cannot be read as different-EEW data and mask sources.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Require the extensions, supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, fflags, or microarchitectural cycles.
VVector Type ConvertFloating-Point
Instruction Behavior
VFWCVT.F.F.V is a RISC-V V-extension VFWCVT widening floating-point/integer conversion instruction with syntax vfwcvt.f.f.v vd, vs2, vm. It executes only for active elements within vl, uses the current SEW for source elements, and writes 2*SEW-wide destination elements; on the base V FP32/FP64 path, this page animation demonstrates SEW=32 inputs producing 64-bit destination results. The encoding uses OP-V, funct6=010010, funct3=001, and VFUNARY0 vs1 selector 01100. A widening FP-to-FP conversion such as binary32 to binary64 is exact; frm validity still follows the vector FP rules; vm=0 uses v0.t as the execution mask and vm=1 is unmasked.
VFWCVT.F.F.V Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 widening conversion lane by lane: each active lane converts the single-width FP value in vs2[i] to a 2*SEW FP value.
Instruction input
vfwcvt.f.f.v
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmexact widening conversion; this context fixes valid frm=RNE
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
dest EEWdestination element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
vs1VFUNARY0 conversion selector
Encoding fields
0x48861257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
01100
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: widen_float(1) -> 1
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
widen_float(1)
1
i=1active
widen_float(1.5)
1.5
i=2skip
v0.t=0, not executed
--
i=3active
widen_float(2.5)
2.5
i=4active
widen_float(-3)
-3
i=5active
widen_float(3.5)
3.5
i=6skip
v0.t=0, not executed
--
i=7active
widen_float(4.5)
4.5
This teaching model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, valid vtype, enabled VS/FS, and ta/ma. Widening single-width integers/finite FP values to the double-width IEEE FP format is exact and independent of rounding mode; this context fixes valid frm=RNE. Inactive/tail elements have no definite displayed values; VL=0 updates no destination elements. NaNs, infinities, fflags, and microarchitectural cycles are outside this model.
Quick Understanding & Search Notes
VFWCVT.F.F.V is best understood as a VFUNARY0 widening conversion: after decoding vs1=01100, active elements convert vs2[i] from an SEW-wide FP value to a 2*SEW-wide FP result.
32-bit OP-V: opcode=1010111, funct3=001, funct6=010010; vs1=01100 is a VFUNARY0 selector, not a second vector source.
vs2 has EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 encodings are reserved, while EMUL≤1 does not require even register numbers. Narrow-source overlap requires source EMUL≥1 and equal highest source/destination register numbers; legal different-EEW overlap forces mask/tail agnostic.
A double-width IEEE FP format exactly represents single-width finite FP values; NaNs still follow scalar FP rules, without guaranteed payload preservation. Every vector FP instruction requires valid frm, even without rounding or at vl=0; invalid frm use is reserved. vxrm does not control these operations.
vm denotes optional v0.t; omission means vm=1, while v0.t means vm=0. Active elements satisfy vstart≤i<vl with the mask enabled. A masked destination cannot overlap v0; one register cannot be read as both data and an EEW=1 mask source.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl, no destination elements, including tails, are updated. Other inactive/tail elements follow vma/vta; ta/ma permits retaining old values or writing all ones, without guaranteed zeros. Successful execution resets vstart=0.
Require the extensions, supported FP widths, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and ta/ma to demonstrate 64-bit results; NaNs, infinities, and fflags are not fully simulated.
Vector Execution Context
Syntax: vfwcvt.f.f.v vd, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=010010. vs1=01100 is a VFUNARY0 selector, not a second vector source.
vs2 has EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved, while EMUL≤1 does not require even register numbers.
Single-width finite FP values widen exactly to the double-width IEEE FP format; NaNs follow scalar FP rules without guaranteed payload preservation. Every vector FP instruction still requires valid frm, including at vl=0; invalid frm use is reserved. vxrm is not used.
Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. A masked destination cannot include v0; one register cannot be read as different-EEW data and mask sources.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Require the extensions, supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, fflags, or microarchitectural cycles.
Common Usage Scenarios
binary32 vectors promoted to binary64
Assume enabled extensions and VS/FS, valid vtype, supported formats, frm=RNE, e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Omit v0.t for unmasked execution: v4(binary32)=[1.5,-2.75,0,3.5] → v2/v3(binary64)=[1.5,-2.75,0,3.5]. Tails follow ta without guaranteed zeros.
mixed-precision FP compute entry
Assume enabled extensions and VS/FS, valid vtype, supported formats, frm=RNE, e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Omit v0.t for unmasked execution: v4(binary32)=[1.5,-2.75,0,3.5] → v2/v3(binary64)=[1.5,-2.75,0,3.5]. Tails follow ta without guaranteed zeros.
higher-precision processing after widening
Assume enabled extensions and VS/FS, valid vtype, supported formats, frm=RNE, e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Omit v0.t for unmasked execution: v4(binary32)=[1.5,-2.75,0,3.5] → v2/v3(binary64)=[1.5,-2.75,0,3.5]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwcvt.f.f.v vd, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=010010. vs1=01100 is a VFUNARY0 selector, not a second vector source.
- vs2 has EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved, while EMUL≤1 does not require even register numbers.
Semantic Check
- Single-width finite FP values widen exactly to the double-width IEEE FP format; NaNs follow scalar FP rules without guaranteed payload preservation. Every vector FP instruction still requires valid frm, including at vl=0; invalid frm use is reserved. vxrm is not used.
- Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. A masked destination cannot include v0; one register cannot be read as different-EEW data and mask sources.
- Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- Require the extensions, supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, fflags, or microarchitectural cycles.
Pitfalls / Common Confusions
vs2 has EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 encodings are reserved, while EMUL≤1 does not require even register numbers. Narrow-source overlap requires source EMUL≥1 and equal highest source/destination register numbers; legal different-EEW overlap forces mask/tail agnostic.
A double-width IEEE FP format exactly represents single-width finite FP values; NaNs still follow scalar FP rules, without guaranteed payload preservation.
The animation's limits are narrower than the architectural legal input domain; represent decimal FP inputs as binary32/binary64 before performing the operation.
FAQ
Where does VFWCVT.F.F.V take its rounding mode from?
The binary32-to-binary64 FP widening path shown here is exact; vector FP instruction frm validity still follows the official rules.
How does VFWCVT.F.F.V use the mask operand?
vm=0 converts only active elements with v0[i]=1; vm=1 is unmasked. Inactive/tail elements follow vma/vta, with legal different-EEW overlap forcing agnostic. At vl=0 or vstart≥vl no destination elements update.
Why does this page animation expose only SEW=32?
The animation focuses on the V 32-bit-source to 64-bit-destination path. V depends on F/D and does not automatically include half precision. Zvfhmin defines the SEW=16 binary16-to-binary32 conversion.