Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFWADD.VV
RISC-V VFWADD.VV Instruction Details
Instruction ManualR-typeAdd SEW float elements of vs2 and vs1, writing widened result (2*SEW) to vd.
Instruction Syntax
vfwadd.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFWADD.VV performs widening floating-point addition. SEW-wide source elements are added and the result is written to a 2*SEW-wide vd. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.
Quick Understanding & Search Notes
VFWADD.VV keeps the add result at wider precision, unlike single-width VFADD.
Widening forms change destination element width and register-group usage, so LMUL/EMUL must be checked.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Vector Execution Context
When reading VFWADD.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
High-Precision Accum
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwadd.vv v2, v4, v6 # 32b->64b».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Dest EMUL=2*LMUL, needs double registers. vd number must be multiple of 2*LMUL.
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.
FAQ
Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.