Does VFWADD.VV use vxrm?
No. This instruction rounds using dynamic FP frm; vxrm controls fixed-point rounding. Only active-element FP exceptions accrue in fflags.
VFWADD.VV
RISC-V VFWADD.VV Instruction Details
Instruction ManualOPFVVVFWADD.VV computes vs2[i] + vs1[i] for active elements, adding in the 2×SEW format and writing the widened result.
Instruction Syntax
vfwadd.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vfwadd.vv vd, vs2, vs1[, v0.t]. Compute vs2[i] + vs1[i] element by element. 32-bit OP-V: funct6=110000, funct3=001, opcode=1010111. Both inputs are SEW wide.
Destination EEW=2×SEW and EMUL=2×LMUL. Narrow inputs widen exactly before double-width addition. Groups with EMUL=2/4/8 align to their size; EMUL≤1 does not require an even start; EMUL>8 is reserved. Narrow-source overlap is legal only with source EMUL≥1 and equal highest source/destination register numbers. Equal-width wide sources may overlap the destination. Legal overlap at different EEWs forces mask/tail agnostic.
Both vs2 and vs1 are vector sources; equal registers read equal initial bits. There is no FP scalar or immediate input.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. A masked destination cannot overlap v0; one source register cannot be read at both data EEW and mask EEW=1.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Dynamic frm controls FP rounding; only active-element exceptions accrue in fflags. vxrm is not used. Valid frm is required even at vl=0; invalid frm use is reserved. V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D. The widening path here is FP32-to-FP64. SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and, with H and virtualization V=1, enabled vsstatus.VS/FS.
The animation fixes LMUL=m1, VLEN=4096, vstart=0, FLEN=64, frm=RNE, and ta/ma. VF scalars at SEW=32 assume valid NaN-boxing. Only finite results are calculated, without NaNs, infinities, overflow, or full fflags; teaching steps are not processor cycles.
VVector OperationsFloating-Point
Instruction Behavior
VFWADD.VV performs widening FP addition. Both inputs are SEW wide. Narrow inputs widen exactly before addition in the 2×SEW format; destination EEW=2×SEW and EMUL=2×LMUL. Results round using dynamic frm; only active-element exceptions accrue in fflags. Fixed-point vxrm is not used. V 1.0 provides FP32/FP64 on RV32/RV64 and depends on F/D; SEW=16 arithmetic requires Zvfh.
VFWADD.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise widening FP addition: SEW=32 sources are widened before writing 2*SEW=64 results.
Instruction input
vfwadd.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
dest EEWdestination element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xc0861257
31..26
25
24..20
19..15
14..12
11..7
6..0
110000
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 + 0.5 -> 1.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 + 0.5
1.5
i=1active
1.5 + 1
2.5
i=2skip
v0.t=0, not executed
--
i=3active
2.5 + 2
4.5
i=4active
-3 + 2.5
-0.5
i=5active
3.5 + 3
6.5
i=6skip
v0.t=0, not executed
--
i=7active
4.5 + 4
8.5
In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, source elements are represented as SEW=32 / binary32, widened exactly to binary64, then addition executes in binary64 before writing the 2*SEW=64 result. This animation uses RNE as a checkable demo mode; NaNs, infinities, and exception flags remain governed by the official RVV FP rules.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, valid vtype, enabled VS/FS, FLEN=64, frm=RNE, and ta/ma. Only SEW=32 FP32-to-FP64 addition is shown; narrow sources widen exactly first. Destination vd..vd+1 must start even, as must the wide .wf vs2 group. A narrow source may overlap the highest destination register; an equal-width wide source may overlap the destination. Equal sources require equal initial bits. VF scalars at SEW=32 assume valid NaN-boxing. VL=0 updates no destination elements, including tails; other inactive/tail values are not specified in this display. Only finite RNE results are calculated, without NaNs, infinities, overflow, invalid NaN boxes, or full fflags; these model limits do not imply illegal architectural FP execution. Steps are not processor cycles.
Quick Understanding & Search Notes
Read each source in its FP format, then add at double width; .wf already has a wide vs2 source.
32-bit OP-V: funct6=110000, funct3=001, opcode=1010111.
The optional assembly operand v0.t means vm=0; omission means vm=1, unmasked.
Widen narrow inputs before double-width addition; do not add at single width before widening the result.
Every vector FP instruction requires valid frm, even at vl=0; use of invalid frm is reserved.
Vector Execution Context
Syntax: vfwadd.vv vd, vs2, vs1[, v0.t]. Compute vs2[i] + vs1[i] element by element. 32-bit OP-V: funct6=110000, funct3=001, opcode=1010111. Both inputs are SEW wide.
Destination EEW=2×SEW and EMUL=2×LMUL. Narrow inputs widen exactly before double-width addition. Groups with EMUL=2/4/8 align to their size; EMUL≤1 does not require an even start; EMUL>8 is reserved. Narrow-source overlap is legal only with source EMUL≥1 and equal highest source/destination register numbers. Equal-width wide sources may overlap the destination. Legal overlap at different EEWs forces mask/tail agnostic.
Both vs2 and vs1 are vector sources; equal registers read equal initial bits. There is no FP scalar or immediate input.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. A masked destination cannot overlap v0; one source register cannot be read at both data EEW and mask EEW=1.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Dynamic frm controls FP rounding; only active-element exceptions accrue in fflags. vxrm is not used. Valid frm is required even at vl=0; invalid frm use is reserved. V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D. The widening path here is FP32-to-FP64. SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and, with H and virtualization V=1, enabled vsstatus.VS/FS.
The animation fixes LMUL=m1, VLEN=4096, vstart=0, FLEN=64, frm=RNE, and ta/ma. VF scalars at SEW=32 assume valid NaN-boxing. Only finite results are calculated, without NaNs, infinities, overflow, or full fflags; teaching steps are not processor cycles.
Common Usage Scenarios
High-Precision Accum
Assume V/VS/FS enabled, valid vtype, supported FP formats, frm=RNE, e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Destination v2/v3 holds binary64 results; vector inputs are binary32. Omitting v0.t makes this unmasked: v4=[1,2,-3,0], v6=[0.5,0.5,0.5,0.5] → v2=[1.5,2.5,-2.5,0.5]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwadd.vv vd, vs2, vs1[, v0.t]. Compute vs2[i] + vs1[i] element by element. 32-bit OP-V: funct6=110000, funct3=001, opcode=1010111. Both inputs are SEW wide.
- Destination EEW=2×SEW and EMUL=2×LMUL. Narrow inputs widen exactly before double-width addition. Groups with EMUL=2/4/8 align to their size; EMUL≤1 does not require an even start; EMUL>8 is reserved. Narrow-source overlap is legal only with source EMUL≥1 and equal highest source/destination register numbers. Equal-width wide sources may overlap the destination. Legal overlap at different EEWs forces mask/tail agnostic.
Semantic Check
- Both vs2 and vs1 are vector sources; equal registers read equal initial bits. There is no FP scalar or immediate input.
- Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. A masked destination cannot overlap v0; one source register cannot be read at both data EEW and mask EEW=1.
- Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- Dynamic frm controls FP rounding; only active-element exceptions accrue in fflags. vxrm is not used. Valid frm is required even at vl=0; invalid frm use is reserved. V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D. The widening path here is FP32-to-FP64. SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and, with H and virtualization V=1, enabled vsstatus.VS/FS.
- The animation fixes LMUL=m1, VLEN=4096, vstart=0, FLEN=64, frm=RNE, and ta/ma. VF scalars at SEW=32 assume valid NaN-boxing. Only finite results are calculated, without NaNs, infinities, overflow, or full fflags; teaching steps are not processor cycles.
Pitfalls / Common Confusions
Destination EEW=2×SEW and EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; fractional EMUL or EMUL=1 does not require even vd. EMUL>8 encodings are reserved.
Active elements satisfy vstart≤i<vl with the execution mask enabled. At vl=0 or vstart≥vl no destination elements change, including tails. ta/ma does not guarantee zeros.
V depends on F/D and supports FP32/FP64; SEW=16 arithmetic requires Zvfh and is not implied by V alone.
The animation computes finite RNE results only; NaNs, infinities, overflow, and full fflags are outside its model. The real instruction follows the official FP rules.
FAQ
Is vm an ordinary assembly immediate?
No. Optional v0.t denotes vm=0, while omission denotes vm=1. Do not write numeric 0 or 1 as an ordinary operand.