Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWADD.VV
RISC-V VWADD.VV Instruction Details
Instruction ManualOPMVVVWADD.VV performs signed widening add; SEW source elements are sign-extended and written as 2*SEW-wide results.
Instruction Syntax
vwadd.vv vd, vs2, vs1, vm
Operand Breakdown
vs2 and vs1 supply SEW sources; vd has EEW=2*SEW and EMUL=2*LMUL<=8. Group starts must align. Wide vd may overlap a narrow source only if source EMUL>=1 and both groups share their highest register; this forces mask/tail agnostic. Equal sources read equal values.
32-bit OP-V: opcode=1010111, funct6=110001, funct3=010 (OPMVV); vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7.
Active vd[i]=sext(vs2[i])+sext(vs1[i]), extending both sources to 2*SEW first. No saturation or vxsat change; old vd is not an accumulator. Require implementation support for source SEW and destination 2*SEW.
Require V 1.0, enabled vector state, vill=0 and supported vtype. Optional v0.t means vm=0; omission means vm=1. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged and inactive/tail follow vma/vta; masked vd excludes v0. v0 cannot supply both EEW=1 mask and data. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.
VVector Operations
Instruction Behavior
vwadd.vv is a RISC-V V extension vector-vector signed widening add instruction. For active elements, the SEW values from vs2 and vs1 are sign-extended to 2*SEW, then added and written to the 2*SEW-wide vd destination.
VWADD.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWADD sign-extends SEW source elements before writing 2*SEW-wide add results to vd.
Instruction input
vwadd.vv
Teaching context: V 1.0, enabled vector state, valid supported vtype; fix LMUL=m1, VLEN=4096 and vstart=0. Require support for source SEW and destination 2*SEW; SEW=64 requires 128-bit integer elements beyond baseline V guarantees. Inputs are nonnegative SEW bit patterns interpreted as signed two’s-complement values; .vx takes low bits for XLEN>SEW, sign-extends for XLEN<SEW, and x0 supplies zero. Masked vd and data sources exclude v0. VL=0 leaves vd unchanged; success resets vstart=0 without changing vxsat. Stages are teaching steps, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. The wide vd destination has EMUL=2 and must start at an even register; if it overlaps a SEW source, that source must be the highest-numbered register in the destination group. Such a legal different-EEW overlap is mask- and tail-agnostic regardless of vtype.vma/vta.In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvwadd.vv
funct6
110001
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
w+
w+
w+
w+
w+
w+
w+
w+
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwadd.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer signed widening addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWADD.VV is not ordinary SEW-wrapping addition: it first sign-extends both source elements, then keeps the addition result in a 2*SEW-wide destination element.
Official syntax is `vwadd.vv vd, vs2, vs1, vm`; vm=1 is unmasked, while vm=0 uses v0.t to select active elements for this instruction.
For this batch's .vv/.vx forms, both source operands are SEW-wide, are sign-extended to 2*SEW, and are then added.
Destination elements are 2*SEW wide and destination EMUL is twice the source EMUL; this is not an accumulator instruction that reads old vd.
Tail elements and masked-off elements follow the current vtype tail/mask policy; the mnemonic alone does not imply fixed zeroing.
Vector Execution Context
When reading VWADD.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Integer Arithmetic
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=8, v12=[127,128,255,0], v4=[1,255,1,255]. v8[0]=128 (0x0080), v8[1]=-129 (0xff7f), v8[3]=-1 (0xffff). Interpret sources as signed two’s-complement values; results are 16-bit. Lane2 and tails keep old values; vxsat stays unchanged. Success resets vstart=0.
Widening Operations
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=8, v12=[127,128,255,0], v4=[1,255,1,255]. v8[0]=128 (0x0080), v8[1]=-129 (0xff7f), v8[3]=-1 (0xffff). Interpret sources as signed two’s-complement values; results are 16-bit. Lane2 and tails keep old values; vxsat stays unchanged. Success resets vstart=0.
Vectorized Loops
Assume enabled V/VS, valid m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=8, v12=[127,128,255,0], v4=[1,255,1,255]. v8[0]=128 (0x0080), v8[1]=-129 (0xff7f), v8[3]=-1 (0xffff). Interpret sources as signed two’s-complement values; results are 16-bit. Lane2 and tails keep old values; vxsat stays unchanged. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPMVV.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Destination elements are 2*SEW wide, so the destination register group EMUL widens too.
Signed forms sign-extend inputs.
This is widening addition, not saturating addition; it does not set vxsat.
FAQ
How is VWADD.VV different from ordinary addition?
VWADD.VV sign-extends SEW source elements and produces a 2*SEW-wide result; ordinary single-width vector addition writes only a SEW-wide result.
Does VWADD.VV read old vd as an accumulator?
No. These .vv/.vx forms write a result formed from current SEW-wide sources; .wv/.wx are wide-vs2-source forms and likewise do not read old vd.