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VWADD.WX

RISC-V VWADD.WX Instruction Details

Q: Is VWADD.WX an accumulator instruction?

No. It forms its result only from the current vs2 and x[rs1] sources and does not read old vd as an accumulator.

Instruction ManualV-type

Signed widening add with 2*SEW results.

Instruction Syntax

vwadd.wx vd, vs2, rs1, vm

Operand Breakdown

vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 has EEW=2*SEW and EMUL=2*LMUL. rs1 is an integer scalar: take low SEW bits for XLEN>SEW or first sign-extend to SEW for XLEN<SEW, including unsigned addition; x0 supplies zero.

32-bit OP-V: opcode=1010111, funct6=110101, funct3=110 (OPMVX); vm is bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. The syntax's final vm denotes optional v0.t; omission is unmasked.

For active elements, sign-extend the SEW second source to 2*SEW before adding to wide vs2; keep low 2*SEW result bits. No old-vd accumulation, saturation or vxsat change. Equal-width vd/vs2 may overlap. Group starts align to EMUL. Wide vd may overlap a narrow source only when source EMUL>=1 and their highest registers match; legal different-EEW overlap forces mask/tail agnostic.

Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported SEW/2*SEW. vm=0 uses v0.t; vm=1 is unmasked. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged and inactive/tail follow vma/vta. Masked vd excludes v0, which cannot supply both EEW=1 mask and data. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.

VVector Operations

Extension condition: Requires RV32/RV64 V 1.0, enabled vector state, vill=0, and support for the selected SEW and 2*SEW element widths; widening SEW=64 needs 128-bit integer element support.

Related Search Terms

vwadd.wx instruction vwadd.wx syntax vwadd.wx encoding signed widening add RVV widening vwadd.wx mask

Instruction Behavior

VWADD.WX adds a signed 2*SEW-wide vs2 source to x[rs1], converted by the XLEN/SEW rule and sign-extended to 2*SEW, then writes a 2*SEW-wide result.

VWADD.WX Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VWADD adds a sign-extended SEW second source to a 2*SEW-wide vs2 value and writes a 2*SEW-wide vd result.

Instruction input

vwadd.wx

vdUse an even start; wide vd has EMUL=2; a narrow overlap must be the highest registervs2Use even v2-v30; v0 supplies the EEW=1 execution maskrs1Use x0-x31 or ABI namevmexecution mask control

Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096 and vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer element support. Enter nonnegative bit patterns: 32-bit vs2 and 16-bit second source. Interpret the narrow source as signed two’s-complement and sign-extend before addition; keep the low 32 result bits. Scalars first follow XLEN/SEW conversion: take low bits when XLEN>SEW and sign-extend when XLEN<SEW, including unsigned addition; x0 supplies zero. Wide vs2 has EMUL=2 and an even start; Equal-width vd/vs2 may overlap. With v0.t, vd and data sources exclude v0. Only body is shown, without definite inactive/tail values; Wide vd has EMUL=2 and an even start; a narrow source can overlap vd only at the destination group’s highest register, forcing agnostic behavior at different EEWs. VL=0 leaves vd unchanged; success resets vstart=0 and leaves vxsat unchanged. Stages are not processor cycles.

Execution Context

VLSEWXLENvs2 elementscomma-separatedx11 valueXLEN=64, converted to SEW by .vx rulesv0 mask bitscontinuous 0/1 bit string

OP-V encodingvwadd.wx

funct6

110101

vs2

01000

rs1

01011

funct3

110

00100

opcode

1010111

lane

0x80000020

0x00007fff

0xffffffee

0x00001020

0x80000020

0x00007fff

0xffffffee

0x00001020

x11

0x0013

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vwadd.wx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer signed widening addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VWADD.WX uses an already 2*SEW-wide vs2 source and adds x[rs1] after XLEN/SEW conversion and sign extension; it does not read old vd.

Destination elements are 2*SEW wide.

In W forms, vs2 is already wide and the second operand is extended from single width before addition.

Signed forms use sign extension.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — V 1.0, §31.5, §31.10–31.11, §31.20

Vector Execution Context

When reading VWADD.WX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Vector Integer Arithmetic

Assume enabled V/VS, valid e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=8, v12=[65535,32767,0,65535], x5=1. v8=[0x0000,0x8000,unchanged,0x0000]; interpret sources as signed two’s-complement and sign-extend, keeping low 16 result bits. Lane2 and tails keep old values; vxsat stays unchanged. Success resets vstart=0.

Widening Operations

Vectorized Loops

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is V-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

In W forms, vs2 is already a 2*SEW-wide source.

The second operand is sign-extended before addition.

Destination elements remain 2*SEW wide.

FAQ

Is VWADD.WX an accumulator instruction?