Is it just add then shift right?
Not exactly. The right shift uses vxrm rounding modes rnu/rne/rdn/rod.
VAADD.VV
RISC-V VAADD.VV Instruction Details
Instruction ManualR-typeVector signed averaging add: vd[i] = roundoff_signed(vs2[i] + vs1[i], 1).
Instruction Syntax
vaadd.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations
Instruction Behavior
vaadd.vv performs vector signed averaging add. The infinite-precision sum vs2[i]+vs1[i] is right-shifted by one bit and rounded according to vxrm, then truncated to SEW bits. There is no result overflow for vaadd/vaaddu.
Quick Understanding & Search Notes
VAADD.VV is an RVV fixed-point averaging add: it adds in infinite precision, right-shifts by one with vxrm rounding, then truncates to an SEW-bit result.
VAADD uses the signed roundoff rule.
vaadd/vaaddu cannot overflow in the result; this differs from saturating add and normal add.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vaadd.vv vd, vs2, vs1».
Data Storing
Understand this scenario with real code like «vaadd.vv vd, vs2, vs1».
Vector Operations
Understand this scenario with real code like «vaadd.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Rounding follows vxrm (rnu/rne/rdn/rod); it is not a fixed '+1 then shift' operation.
vasub/vasubu ignore overflow and wrap; vaadd/vaaddu have no result overflow.
FAQ
Does it set vxsat?
Not for result overflow; averaging add cannot overflow by definition.