Check vl first
Body elements satisfy vstart ≤ i < vl; when vstart≥vl, no destination elements are updated. The example uses vsetvli to select vl and vtype.
VAADD.VV
RISC-V VAADD.VV Instruction Details
Instruction ManualOPMVV (OP-V)vector-vector signed averaging add: active elements read vs2 and vs1, round according to vxrm, and write the SEW-width vd result.
Instruction Syntax
vaadd.vv vd, vs2, vs1, vm
Operand Breakdown
vd: vector register group receiving SEW-width averaging-add results; vs2: first SEW-width vector source.
vs1: second SEW-width vector source; equal sources read the same initial elements.
Interpret signedness as specified for this instruction, add in infinite precision, then shift right by one and round using vxrm; no overflow or vxsat update occurs.
Require V and support for the selected vtype; only active body elements execute. vm=0 uses v0.t and vm=1 is unmasked; masked vd cannot overlap v0, and v0 cannot be read as both mask and different-EEW data.
VVector Operations
Instruction Behavior
vaadd.vv adds two signed SEW-width sources in infinite precision, then shifts right by one and rounds using vxrm (rnu/rne/rdn/rod), writing SEW-width vd. The result cannot overflow; it neither saturates nor sets vxsat. With vm=0, v0.t enables active elements where vstart ≤ i < vl.
VAADD.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VAADD interprets elements as signed, sums them, rounds the one-bit average with vxrm, and writes vd.
Instruction input
vaadd.vv
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvaadd.vv
funct6
001001
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0021
0x007f
0x0080
0x00f1
0x0012
0x00fe
0x0021
0x007f
avg+
avg+
avg+
avg+
avg+
avg+
avg+
avg+
v12
0x0011
0x0001
0x0080
0x000f
0x0020
0x007d
0x0011
0x0001
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vaadd.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed averaging addition, vxrm fixed-point rounding, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VAADD.VV averages signed source elements using vxrm rounding, writing SEW-width vd without saturation.
vaadd.vv uses the 32-bit OPMVV encoding: opcode=1010111, funct3=010, funct6=001001.
Averaging add rounds the one-bit shift of the infinite-precision sum; the specification states that VAADD/VAADDU cannot overflow in the result.
The rounding mode comes from the fixed-point rounding mode CSR vxrm: rnu, rne, rdn, or rod.
Only active body elements within vl are processed; vm=0 uses v0.t, and tail or masked-off destination elements follow vtype policies.
Vector Execution Context
When reading VAADD.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
With vm=0, v0.t selects active body elements; omitting the mask operand means vm=1, unmasked. Inactive and tail elements follow current vma/vta.
Common Usage Scenarios
Fixed-point averaging
Assume V with e16,m1, x10 holding the requested element count, and initialized vector sources, vxrm and v0 mask (also x11 for .vx). vsetvli selects vl; averaging add updates active body elements, while ta/ma permit agnostic tail and inactive values.
Vector data processing
Assume V with e16,m1, x10 holding the requested element count, and initialized vector sources, vxrm and v0 mask (also x11 for .vx). vsetvli selects vl; averaging add updates active body elements, while ta/ma permit agnostic tail and inactive values.
RVV masked execution
Assume V with e16,m1, x10 holding the requested element count, and initialized vector sources, vxrm and v0 mask (also x11 for .vx). vsetvli selects vl; averaging add updates active body elements, while ta/ma permit agnostic tail and inactive values.
Pre-Use Checklist
Syntax Check
- vd: vector register group receiving SEW-width averaging-add results; vs2: first SEW-width vector source.
- vs1: second SEW-width vector source; equal sources read the same initial elements.
Semantic Check
- Interpret signedness as specified for this instruction, add in infinite precision, then shift right by one and round using vxrm; no overflow or vxsat update occurs.
- Require V and support for the selected vtype; only active body elements execute. vm=0 uses v0.t and vm=1 is unmasked; masked vd cannot overlap v0, and v0 cannot be read as both mask and different-EEW data.
Pitfalls / Common Confusions
Rounding is controlled by vxrm; this is not a fixed add-one-then-shift operation.
The VAADD/VAADDU averaging-add result cannot overflow by definition; this is not saturating add.
When vm=0, v0.t controls active elements; masked-off and tail elements follow the current vtype policies.
FAQ
How is VAADD.VV different from ordinary VADD?
VAADD.VV is fixed-point averaging add and rounds the one-bit shifted result with vxrm; ordinary integer add does not use vxrm.
Does VAADD.VV set vxsat?
No. This instruction uses vxrm rounding but is not a saturating instruction; use saturating fixed-point instructions such as VSADD/VSSUB when saturation is required.