Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VAADD.VV
RISC-V VAADD.VV Instruction Details
Instruction ManualR-typevector-vector signed averaging add: active elements read vs2 and vs1, round according to vxrm, and write the SEW-width vd result.
Instruction Syntax
vaadd.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Instruction Behavior
vaadd.vv is an RVV fixed-point averaging add instruction. It operates on active elements within vl, uses the vxrm rnu/rne/rdn/rod rounding mode, and is controlled by vm/v0.t masking.
VAADD.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VAADD interprets elements as signed, sums them, rounds the one-bit average with vxrm, and writes vd.
Instruction input
vaadd.vv
OP-V encodingvaadd.vv
funct6
001001
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0021
0x007f
0x0080
0x00f1
0x0012
0x00fe
0x0021
0x007f
avg+
avg+
avg+
avg+
avg+
avg+
avg+
avg+
v12
0x0011
0x0001
0x0080
0x000f
0x0020
0x007d
0x0011
0x0001
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vaadd.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed averaging addition, vxrm fixed-point rounding, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VAADD.VV is RVV fixed-point averaging add. Source elements are interpreted as signed values, the result is rounded by vxrm and written to the SEW-width vd element; it does not set floating-point exception flags and is not a saturating instruction.
vaadd.vv vd, vs2, vs1, vm uses OP-V encoding; the .vv form is selected by funct3 and funct6 selects VAADD.
Averaging add rounds the one-bit shift of the infinite-precision sum; the specification states that VAADD/VAADDU cannot overflow in the result.
The rounding mode comes from the fixed-point rounding mode CSR vxrm: rnu, rne, rdn, or rod.
Only active body elements within vl are processed; vm=0 uses v0.t, and tail or masked-off destination elements follow vtype policies.
Vector Execution Context
When reading VAADD.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Fixed-point averaging
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vaadd.vv v4, v8, v12, v0.t».
Vector data processing
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vaadd.vv v4, v8, v12, v0.t».
RVV masked execution
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vaadd.vv v4, v8, v12, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Rounding is controlled by vxrm; this is not a fixed add-one-then-shift operation.
The VAADD/VAADDU averaging-add result cannot overflow by definition; this is not saturating add.
When vm=0, v0.t controls active elements; masked-off and tail elements follow the current vtype policies.
FAQ
How is VAADD.VV different from ordinary VADD?
VAADD.VV is fixed-point averaging add and rounds the one-bit shifted result with vxrm; ordinary integer add does not use vxrm.
Does VAADD.VV set vxsat?
No. This instruction uses vxrm rounding but is not a saturating instruction; use saturating fixed-point instructions such as VSADD/VSSUB when saturation is required.