Check vl first
Body elements satisfy vstart ≤ i < vl; vstart≥vl leaves the destination unchanged. Set supported vl/vtype and initialize the sources and v0 first.
VASUB.VV
RISC-V VASUB.VV Instruction Details
Instruction ManualOPMVVVASUB.VV rounds signed averaging subtraction with vxrm and writes SEW-bit active-element results.
Instruction Syntax
vasub.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is allowed and equal sources read identical initial values.
vs1 supplies the second SEW-bit vector source at the same lane.
Require V and supported vtype. Active body: vstart≤i<vl and (vm=1 or v0.mask[i]=1); vstart≥vl leaves the destination unchanged.
Omitting the mask means vm=1; v0.t means vm=0. Inactive/tail follow vma/vta; masked vd cannot cover v0, and v0 cannot be read at both EEW=1 and SEW.
VVector OperationsFixed-Point Arithmetic
Instruction Behavior
Require V and supported vtype. Active elements compute roundoff_signed(signed(vs2[i]) - signed(vs1[i]), 1), retaining low SEW bits. vs1[i] supplies the second SEW-bit source. Body: vstart≤i<vl. vm=0 selects with v0.t; omitting the mask means vm=1. Inactive/tail elements follow vma/vta.
VASUB.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VASUB uses the infinite-precision difference for averaging subtract, rounds with vxrm, and writes the SEW-width vd result; final overflow wraps as specified.
Instruction input
vasub.vv
Require valid vtype, enabled VS, and supported SEW; VL=0 updates nothing, including tails. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvasub.vv
funct6
001011
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0021
0xfff8
0x0080
0x00f1
0xffef
0x00fe
0x0021
0xffe6
avg-
avg-
avg-
avg-
avg-
avg-
avg-
avg-
v12
0x0005
0x0041
0x0090
0x0002
0x007f
0x0013
0x0005
0x0041
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vasub.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed averaging subtraction, vxrm fixed-point rounding, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
roundoff_signed(signed(vs2[i]) - signed(vs1[i]), 1); form the infinite-precision signed difference, round with vxrm, then wrap any final overflow.
32-bit OP-V: opcode=1010111, funct6=001011, funct3=010 (OPMVV).
Active body: vstart≤i<vl and (unmasked or v0.mask[i]=1); vstart≥vl leaves the destination unchanged.
vxrm: rnu nearest-up, rne nearest-even, rdn down, rod odd; use (difference >> 1) + r.
Vector Execution Context
When reading VASUB.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
With vm=0, v0.t selects active body elements; omitting the mask operand means vm=1, unmasked. Inactive and tail elements follow current vma/vta.
Common Usage Scenarios
Fixed-point averaging subtraction with vxrm rounding
Assume V with e8,m1, x10=4 giving vl=4, vstart=0, source lanes initialized to vs2=127, vs1=128, vxrm=rne, and v0 bits 1010 in lane order 0..3. vsetvli x5, x10, e8, m1, ta, ma vasub.vv v4, v8, v12, v0.t gives [128,policy,128,policy]; policy follows vma and tails follow vta. 127-(-128)=255; rne rounds 127.5 to 128, wrapping to -128 (0x80) at 8 bits.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is allowed and equal sources read identical initial values.
- vs1 supplies the second SEW-bit vector source at the same lane.
Semantic Check
- Require V and supported vtype. Active body: vstart≤i<vl and (vm=1 or v0.mask[i]=1); vstart≥vl leaves the destination unchanged.
- Omitting the mask means vm=1; v0.t means vm=0. Inactive/tail follow vma/vta; masked vd cannot cover v0, and v0 cannot be read at both EEW=1 and SEW.
Pitfalls / Common Confusions
Compute the signed difference in infinite precision before the one-bit shift and vxrm rounding; do not truncate the difference first.
Largest positive minus smallest negative can overflow after rnu/rne rounding and wrap; no saturation or vxsat update.
Masked vd cannot overlap v0; v0 cannot supply both the EEW=1 mask and SEW data.
FAQ
How does VASUB.VV handle inactive elements?
Follow vma: undisturbed or agnostic, not fixed zero. Tails follow vta.
Does VASUB.VV saturate?
No; retain low SEW bits without setting vxsat.