Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VASUB.VV
RISC-V VASUB.VV Instruction Details
Instruction ManualR-typevector-vector signed averaging subtract: active elements read vs2 and vs1, round according to vxrm, and write the SEW-width vd result.
Instruction Syntax
vasub.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsFixed-Point Arithmetic
Instruction Behavior
vasub.vv is an RVV fixed-point averaging subtract instruction. It operates on active elements within vl, uses the vxrm rnu/rne/rdn/rod rounding mode, and is controlled by vm/v0.t masking.
VASUB.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VASUB uses the infinite-precision difference for averaging subtract, rounds with vxrm, and writes the SEW-width vd result; final overflow wraps as specified.
Instruction input
vasub.vv
OP-V encodingvasub.vv
funct6
001011
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0021
0xfff8
0x0080
0x00f1
0xffef
0x00fe
0x0021
0xffe6
avg-
avg-
avg-
avg-
avg-
avg-
avg-
avg-
v12
0x0005
0x0041
0x0090
0x0002
0x007f
0x0013
0x0005
0x0041
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vasub.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed averaging subtraction, vxrm fixed-point rounding, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VASUB.VV is RVV fixed-point averaging subtract. Source elements are interpreted as signed values, the result is rounded by vxrm and written to the SEW-width vd element; it does not set floating-point exception flags and is not a saturating instruction.
vasub.vv vd, vs2, vs1, vm uses OP-V encoding; the .vv form is selected by funct3 and funct6 selects VASUB.
Averaging subtract rounds the one-bit shift of the infinite-precision difference; the specification states that VASUB/VASUBU ignore overflow and wrap.
The rounding mode comes from the fixed-point rounding mode CSR vxrm: rnu, rne, rdn, or rod.
Only active body elements within vl are processed; vm=0 uses v0.t, and tail or masked-off destination elements follow vtype policies.
Vector Execution Context
When reading VASUB.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Fixed-point averaging
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vasub.vv v4, v8, v12, v0.t».
Vector data processing
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vasub.vv v4, v8, v12, v0.t».
RVV masked execution
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vasub.vv v4, v8, v12, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Rounding is controlled by vxrm; this is not a fixed add-one-then-shift operation.
VASUB/VASUBU compute the pre-rounding difference in infinite precision; if the averaging-subtract result overflows, the final SEW-width result wraps.
When vm=0, v0.t controls active elements; masked-off and tail elements follow the current vtype policies.
FAQ
How is VASUB.VV different from ordinary VSUB?
VASUB.VV is fixed-point averaging subtract and rounds the one-bit shifted result with vxrm; ordinary integer subtract does not use vxrm.
Does VASUB.VV set vxsat?
No. This instruction uses vxrm rounding but is not a saturating instruction; use saturating fixed-point instructions such as VSADD/VSSUB when saturation is required.