VSSRA.VV

RISC-V VSSRA.VV Instruction Details

Instruction ManualR-type

Element-wise scaling arithmetic right shift.

Instruction Syntax

vssra.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations

Instruction Behavior

VSSRA.VV applies an element-wise scaling arithmetic right shift using the shift amount from vs1[i] and writes vd. Scaling shifts use vxrm to round shifted-out bits.

Quick Understanding & Search Notes

VSSRA.VV is a fixed-point scaling vector shift instruction; the shift amount uses only the architecturally specified low bits.

VSSRL/VSSRA use vxrm to round shifted-out bits.
Arithmetic right shift preserves sign-extension semantics.
VI/VV/VX forms take shift amounts from an immediate, vector elements, or a scalar register respectively.

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «vssra.vv v8, v12, v4, v0.t».

Data Storing

Understand this scenario with real code like «vssra.vv v8, v12, v4, v0.t».

Vector Operations

Understand this scenario with real code like «vssra.vv v8, v12, v4, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is a rounding/scaling shift, not a saturating shift.
Rounding follows vxrm; vxsat is not set by this instruction.

FAQ

Does VSSRA.VV set vxsat?

Scaling shifts use vxrm rounding but are not saturating clip instructions; use VNCLIP for saturating narrowing.