How is VSSRL.VV different from VSRL?
VSSRL.VV rounds shifted-out bits according to vxrm during the right shift; VSRL is an ordinary right shift and does not use vxrm.
VSSRL.VV
RISC-V VSSRL.VV Instruction Details
Instruction ManualOPIVVVSSRL.VV logically right-shifts active elements with vxrm rounding, using low lg2(SEW) bits of vs1[i].
Instruction Syntax
vssrl.vv vd, vs2, vs1, vm
Operand Breakdown
vd/vs2/vs1 are EEW=SEW, EMUL=LMUL vector groups with legal aligned starts. Equal-width source/destination overlap is allowed; equal sources read equal initial values. vs1[i] supplies per-element shift counts.
32-bit OP-V: opcode=1010111, funct6=101010, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7. Omit v0.t for vm=1; include it for vm=0.
d uses only low lg2(SEW) count bits. Logical right-shift an unsigned value, then apply vxrm as (v >> d)+r: rnu nearest-up, rne nearest-even, rdn down, rod odd. d=0 retains the input. No saturation or vxsat change.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW. Only active vstart<=i<vl elements compute; prestart is unchanged, inactive/tail follow vma/vta, retaining old values or becoming all ones. vstart>=vl (including vl=0) updates no destination elements. Masked vd excludes v0; v0 cannot supply both EEW=1 mask and SEW data. Normal completion resets vstart=0; implementations may reject nonzero vstart values they cannot produce.
VVector Operations
Instruction Behavior
VSSRL.VV is a V 1.0 single-width fixed-point scaling logical right shift. For active elements, d uses only low lg2(SEW) bits of vs1[i]; vd receives (unsigned(vs2[i]) >> d) plus the vxrm rounding increment. d=0 retains the input. No saturation or vxsat change occurs.
VSSRL.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSSRL takes the low shift-count bits, rounds shifted-out bits with vxrm, and performs a fixed-point logical scaling shift.
Instruction input
vssrl.vv
Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW, LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Equal-width source/destination overlap is legal; equal source registers require equal elements. With v0.t, vd/vs2/vs1 cannot be v0. Use low log2(SEW) shift-count bits and keep low SEW result bits; inactive/tail values are not specified here. Enter nonnegative SEW bit patterns; interpret VSSRA as two’s-complement signed and VSSRL as unsigned, then round using vxrm; vxsat is unchanged. d=0 applies no rounding. x0 supplies zero; normal completion resets vstart=0. VL=0 leaves the destination unchanged; stages are not processor cycles.
Execution Context
Shift-count rule: only the low lg2(SEW) bits of the corresponding vs1 element are used.
OP-V encodingvssrl.vv
funct6
101010
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0035
0x007f
0x0080
0x0123
0x00ff
0x0019
0x0035
0x007f
round>>
round>>
round>>
round>>
round>>
round>>
round>>
round>>
v12
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0001
0x0002
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vssrl.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows OP-V decode, low-bit shift-count selection, per-element right shifts, and destination writeback; it does not model pipelines or timing.
Quick Understanding & Search Notes
Shift vs2[i] logically by the effective count from vs1[i], then round with vxrm; this is a same-width result.
32-bit OP-V: opcode=1010111, funct6=101010, funct3=000. vm=0 uses v0.t; omission means vm=1.
d uses only low lg2(SEW) count bits. vxrm selects rnu nearest-up, rne nearest-even, rdn down or rod odd; d=0 does not round. vxsat stays unchanged.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW. Only active vstart<=i<vl computes; prestart is unchanged, inactive/tail follow vma/vta. vstart>=vl (including vl=0) leaves vd unchanged; success resets vstart=0.
vd/vs2/vs1 have EEW=SEW, EMUL=LMUL and aligned group starts. Equal-width source/destination overlap is allowed; equal sources read equal values.
Masked vd excludes v0; v0 cannot supply both the EEW=1 mask and SEW data.
Vector Execution Context
vd/vs2/vs1 are EEW=SEW, EMUL=LMUL vector groups with legal aligned starts. Equal-width source/destination overlap is allowed; equal sources read equal initial values. vs1[i] supplies per-element shift counts.
32-bit OP-V: opcode=1010111, funct6=101010, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7. Omit v0.t for vm=1; include it for vm=0.
d uses only low lg2(SEW) count bits. Logical right-shift an unsigned value, then apply vxrm as (v >> d)+r: rnu nearest-up, rne nearest-even, rdn down, rod odd. d=0 retains the input. No saturation or vxsat change.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW. Only active vstart<=i<vl elements compute; prestart is unchanged, inactive/tail follow vma/vta, retaining old values or becoming all ones. vstart>=vl (including vl=0) updates no destination elements. Masked vd excludes v0; v0 cannot supply both EEW=1 mask and SEW data. Normal completion resets vstart=0; implementations may reject nonzero vstart values they cannot produce.
Common Usage Scenarios
Fixed-point scaling
Assume enabled V/VS, valid e8,m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, vxrm=rne, v0.mask[0..3]=1111, v12=[1,127,128,255], and v4=[3,3,3,3]. d=3; nearest-even rounding gives v8=[0,16,16,32]. Sources, inactive/tail values and vxsat stay unchanged; normal completion resets vstart=0.
Vector shifts
Assume enabled V/VS, valid e8,m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, vxrm=rne, v0.mask[0..3]=1111, v12=[1,127,128,255], and v4=[3,3,3,3]. d=3; nearest-even rounding gives v8=[0,16,16,32]. Sources, inactive/tail values and vxsat stay unchanged; normal completion resets vstart=0.
DSP data paths
Assume enabled V/VS, valid e8,m1,tu,mu, VLEN=4096, XLEN=64, vl=4, vstart=0, vxrm=rne, v0.mask[0..3]=1111, v12=[1,127,128,255], and v4=[3,3,3,3]. d=3; nearest-even rounding gives v8=[0,16,16,32]. Sources, inactive/tail values and vxsat stay unchanged; normal completion resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd/vs2/vs1 are EEW=SEW, EMUL=LMUL vector groups with legal aligned starts. Equal-width source/destination overlap is allowed; equal sources read equal initial values. vs1[i] supplies per-element shift counts.
- 32-bit OP-V: opcode=1010111, funct6=101010, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7. Omit v0.t for vm=1; include it for vm=0.
Semantic Check
- d uses only low lg2(SEW) count bits. Logical right-shift an unsigned value, then apply vxrm as (v >> d)+r: rnu nearest-up, rne nearest-even, rdn down, rod odd. d=0 retains the input. No saturation or vxsat change.
- Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported vtype/SEW. Only active vstart<=i<vl elements compute; prestart is unchanged, inactive/tail follow vma/vta, retaining old values or becoming all ones. vstart>=vl (including vl=0) updates no destination elements. Masked vd excludes v0; v0 cannot supply both EEW=1 mask and SEW data. Normal completion resets vstart=0; implementations may reject nonzero vstart values they cannot produce.
Pitfalls / Common Confusions
VSSRL rounds shifted-out bits with vxrm; it is not an ordinary VSRL right shift.
The instruction does not saturate or set vxsat; use VNCLIP/VNCLIPU for saturating narrowing shifts.
The VV form takes the shift count from the same-lane vs1 element; the effective shift count uses the SEW-selected low bits.
FAQ
Does VSSRL.VV set vxsat?
No. VSSRL does not saturate; vxsat retains its prior value and is not cleared.