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VSSRL.VV

RISC-V VSSRL.VV Instruction Details

Instruction ManualR-type

VSSRL.VV performs an element-wise fixed-point rounding logical right shift using a shift count from the same-lane vs1 element.

Instruction Syntax

vssrl.vv vd, vs2, vs1, vm
Operand Breakdown
vs3: source vector register group providing active elements to store.
rs1: integer base-address register; unit-stride forms write consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Related Search Terms
VSSRL.VV instructionvssrl.vv syntaxvssrl.vv encodingRVV scaling shiftvxrm roundinglogical right shift

Instruction Behavior

VSSRL.VV is a RISC-V V extension fixed-point scaling shift. It reads active vs2 elements, uses the low shift-count bits from the same-lane vs1 element, rounds shifted-out bits according to vxrm, and writes the SEW-width result to vd.

VSSRL.VV Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VSSRL takes the low shift-count bits, rounds shifted-out bits with vxrm, and performs a fixed-point logical scaling shift.

Instruction input
vssrl.vv
OP-V encodingvssrl.vv
funct6
101010
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0035
0x007f
0x0080
0x0123
0x00ff
0x0019
0x0035
0x007f
round>>
round>>
round>>
round>>
round>>
round>>
round>>
round>>
v12
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0001
0x0002
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step

Show OP-V 32-bit encoding fields

vssrl.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer scaling logical right shift, vxrm fixed-point rounding, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VSSRL.VV is an RVV fixed-point scaling operation: active lanes take values from vs2, take the shift count from the same-lane vs1 element, apply vxrm rounding, and write vd.

Official syntax is `vssrl.vv vd, vs2, vs1, vm`; vm selects unmasked execution or v0.t masking.
VSSRL uses the V extension fixed-point rounding-mode CSR vxrm, with rnu, rne, rdn, and rod modes.
The logical right-shift result is written at SEW width; inactive elements follow the current vtype mask/tail policy.
VSSRL does not set vxsat, unlike the saturating narrowing behavior of VNCLIP/VNCLIPU.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VSSRL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Fixed-point scaling

Understand this scenario with real code like «vssrl.vv v8, v12, v4, v0.t».

Vector shifts

Understand this scenario with real code like «vssrl.vv v8, v12, v4, v0.t».

DSP data paths

Understand this scenario with real code like «vssrl.vv v8, v12, v4, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

VSSRL rounds shifted-out bits with vxrm; it is not an ordinary VSRL right shift.
The instruction does not saturate or set vxsat; use VNCLIP/VNCLIPU for saturating narrowing shifts.
The VV form takes the shift count from the same-lane vs1 element; the effective shift count uses the SEW-selected low bits.

FAQ

How is VSSRL.VV different from VSRL?

VSSRL.VV rounds shifted-out bits according to vxrm during the right shift; VSRL is an ordinary right shift and does not use vxrm.

Does VSSRL.VV set vxsat?

No. VSSRL.VV is a fixed-point rounding scaling shift, not a saturating clip instruction.