Can the VSRL.VV shift count exceed SEW?
The encoded or source value can be wider, but ordinary RVV shifts use only the low log2(SEW) bits selected by SEW as the actual shift count.
VSRL.VV
RISC-V VSRL.VV Instruction Details
Instruction ManualOPIVVElement-wise logical right shift.
Instruction Syntax
vsrl.vv vd, vs2, vs1, vm
Operand Breakdown
V 1.0 requires enabled vector state, vill=0 and supported vtype/SEW. vd/vs2/vs1 are aligned EEW=SEW, EMUL=LMUL groups. vs1[i] supplies per-element counts; equal source registers need equal initial values.
32-bit OP-V: opcode=1010111, funct6=101000, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7. shamt uses only low lg2(SEW) bits. Logical right shift fills high bits with zero. No vxrm rounding or vxsat change.
Optional v0.t means vm=0; omission means vm=1. Masked vd excludes v0; v0 cannot supply both EEW=1 mask and SEW data. Equal-width source/destination overlap is allowed. Compute active vstart<=i<vl only; prestart is unchanged, inactive/tail follow vma/vta; vstart>=vl (including vl=0) leaves the destination unchanged. Success resets vstart=0.
VVector Operations
Instruction Behavior
VSRL.VV performs RVV single-width integer logical right shift. Each active element reads vs2[i], takes the shift amount from vs1[i], uses only the low bits selected by SEW as specified by the V extension, and writes the result to vd. With vm=0, v0.t selects which body elements participate in this shift.
VSRL.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSRL takes the low shift-count bits, shifts active elements right logically, and fills high bits with zero.
Instruction input
vsrl.vv
Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW, LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Equal-width source/destination overlap is legal; equal source registers require equal elements. With v0.t, vd/vs2/vs1 cannot be v0. Use low log2(SEW) shift-count bits and keep low SEW result bits; inactive/tail values are not specified here. VL=0 leaves the destination unchanged; stages are not processor cycles.
Execution Context
Shift-count rule: only the low lg2(SEW) bits of the corresponding vs1 element are used.
OP-V encodingvsrl.vv
funct6
101000
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
>>
>>
>>
>>
>>
>>
>>
>>
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vsrl.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows OP-V decode, low-bit shift-count selection, per-element right shifts, and destination writeback; it does not model pipelines or timing.
Quick Understanding & Search Notes
VSRL.VV applies logical right shift lane by lane to active elements within the current vl. The full shift source is not used as a count directly; the count uses only the low log2(SEW) bits, and mask-off or tail elements follow the current vtype policies.
VSRL uses OP-V vector-arithmetic encoding with funct6=101000; the .vv form is selected by funct3=000.
The VV form takes each lane shift-count source from the corresponding vs1[i] element. The actual count uses only the low log2(SEW) bits.
VSRL.VV shifts right logically and fills high bits with zero; it shifts the unsigned bit pattern right. Ordinary VSLL/VSRL/VSRA do not use vxrm rounding and do not set vxsat.
vm=0 uses the v0 mask and vm=1 is unmasked; mask-off body elements and tail elements follow the current mask/tail policy.
Vector Execution Context
V 1.0 requires enabled vector state, vill=0 and supported vtype/SEW. vd/vs2/vs1 are aligned EEW=SEW, EMUL=LMUL groups. vs1[i] supplies per-element counts; equal source registers need equal initial values.
32-bit OP-V: opcode=1010111, funct6=101000, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7. shamt uses only low lg2(SEW) bits. Logical right shift fills high bits with zero. No vxrm rounding or vxsat change.
Optional v0.t means vm=0; omission means vm=1. Masked vd excludes v0; v0 cannot supply both EEW=1 mask and SEW data. Equal-width source/destination overlap is allowed. Compute active vstart<=i<vl only; prestart is unchanged, inactive/tail follow vma/vta; vstart>=vl (including vl=0) leaves the destination unchanged. Success resets vstart=0.
Common Usage Scenarios
Bit Operations & Masks
Assume enabled V/VS, valid supported vtype, LMUL=m1, VLEN=4096, XLEN=64, vstart=0, initialized sources and all body mask bits enabled. SEW=8, vl=4, v4=[3,3,3,3], v12=[1,127,128,255] → v8=[0,15,16,31]. Inactive/tail follow vma/vta without guaranteed zeroing. Success resets vstart=0.
Vector Operations
Assume enabled V/VS, valid supported vtype, LMUL=m1, VLEN=4096, XLEN=64, vstart=0, initialized sources and all body mask bits enabled. SEW=8, vl=4, v4=[3,3,3,3], v12=[1,127,128,255] → v8=[0,15,16,31]. Inactive/tail follow vma/vta without guaranteed zeroing. Success resets vstart=0.
Bitfield Ops
Assume enabled V/VS, valid supported vtype, LMUL=m1, VLEN=4096, XLEN=64, vstart=0, initialized sources and all body mask bits enabled. SEW=8, vl=4, v4=[3,3,3,3], v12=[1,127,128,255] → v8=[0,15,16,31]. Inactive/tail follow vma/vta without guaranteed zeroing. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- V 1.0 requires enabled vector state, vill=0 and supported vtype/SEW. vd/vs2/vs1 are aligned EEW=SEW, EMUL=LMUL groups. vs1[i] supplies per-element counts; equal source registers need equal initial values.
- 32-bit OP-V: opcode=1010111, funct6=101000, funct3=000; vm at bit25, vs2 at bits24:20, vs1 at bits19:15, vd at bits11:7. shamt uses only low lg2(SEW) bits. Logical right shift fills high bits with zero. No vxrm rounding or vxsat change.
Semantic Check
- Optional v0.t means vm=0; omission means vm=1. Masked vd excludes v0; v0 cannot supply both EEW=1 mask and SEW data. Equal-width source/destination overlap is allowed. Compute active vstart<=i<vl only; prestart is unchanged, inactive/tail follow vma/vta; vstart>=vl (including vl=0) leaves the destination unchanged. Success resets vstart=0.
Pitfalls / Common Confusions
Do not treat the full VSRL.VV shift source as the shift count; the actual count uses only the low bits specified by SEW.
VSRL.VV is an ordinary integer shift; it does not use vxrm rounding and does not set vxsat because bits were shifted out.
A mask-off body element is not a deterministic zero write; the destination element follows the current mask policy.
FAQ
How is VSRL.VV different from nearby shift instructions?
VSRL shifts right logically and fills high bits with zero; VSRA shifts right arithmetically and extends the signed element sign bit.