Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSRL.VI
RISC-V VSRL.VI Instruction Details
Instruction ManualV-typeElement-wise logical right shift.
Instruction Syntax
vsrl.vi vd, vs2, uimm, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Instruction Behavior
VSRL.VI performs RVV single-width integer logical right shift. Each active element reads vs2[i], takes the shift amount from uimm, uses only the low bits selected by SEW as specified by the V extension, and writes the result to vd. With vm=0, v0.t selects which body elements participate in this shift.
VSRL.VI Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSRL takes the low shift-count bits, shifts active elements right logically, and fills high bits with zero.
Instruction input
vsrl.vi
immediate value
4 -> shamt 4
5-bit unsigned uimm; shift count uses low lg2(SEW) bitsOP-V encodingvsrl.vi
funct6
101000
vm
0
vs2
01000
uimm
00100
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
>>
>>
>>
>>
>>
>>
>>
>>
imm
0x0004
0x0004
0x0004
0x0004
0x0004
0x0004
0x0004
0x0004
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vsrl.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the uimm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer logical right shift, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VSRL.VI applies logical right shift lane by lane to active elements within the current vl. The full shift source is not used as a count directly; the count uses only the low log2(SEW) bits, and mask-off or tail elements follow the current vtype policies.
VSRL uses OP-V vector-arithmetic encoding with funct6=101000; the .vi form is selected by funct3=011.
The VI form uses the 5-bit unsigned uimm field as the shift-count source. The actual count uses only the low log2(SEW) bits.
VSRL.VI shifts right logically and fills high bits with zero; it shifts the unsigned bit pattern right. Ordinary VSLL/VSRL/VSRA do not use vxrm rounding and do not set vxsat.
vm=0 uses the v0 mask and vm=1 is unmasked; mask-off body elements and tail elements follow the current mask/tail policy.
Vector Execution Context
When reading VSRL.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsrl.vi v8, v12, 3, v0.t».
Vector Operations
Understand this scenario with real code like «vsrl.vi v8, v12, 3, v0.t».
Bitfield Ops
Understand this scenario with real code like «vsrl.vi v8, v12, 3, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Do not treat the full VSRL.VI shift source as the shift count; the actual count uses only the low bits specified by SEW.
VSRL.VI is an ordinary integer shift; it does not use vxrm rounding and does not set vxsat because bits were shifted out.
A mask-off body element is not a deterministic zero write; the destination element follows the current mask policy.
FAQ
Can the VSRL.VI shift count exceed SEW?
The encoded or source value can be wider, but ordinary RVV shifts use only the low log2(SEW) bits selected by SEW as the actual shift count.
How is VSRL.VI different from nearby shift instructions?
VSRL shifts right logically and fills high bits with zero; VSRA shifts right arithmetically and extends the signed element sign bit.