VSRL.VI

RISC-V VSRL.VI Instruction Details

Instruction ManualV-type

Element-wise logical right shift.

Instruction Syntax

vsrl.vi vd, vs2, uimm, vm

Operand Breakdown

V 1.0 requires enabled vector state, vill=0 and supported vtype/SEW. vd/vs2 are aligned EEW=SEW, EMUL=LMUL groups. uimm is zero-extended, 5-bit, 0–31; SEW=64 still cannot encode 32–63.

32-bit OP-V: opcode=1010111, funct6=101000, funct3=011; vm at bit25, vs2 at bits24:20, uimm at bits19:15, vd at bits11:7. shamt uses only low lg2(SEW) bits. Logical right shift fills high bits with zero. No vxrm rounding or vxsat change.

Optional v0.t means vm=0; omission means vm=1. Masked vd excludes v0; v0 cannot supply both EEW=1 mask and SEW data. Equal-width source/destination overlap is allowed. Compute active vstart<=i<vl only; prestart is unchanged, inactive/tail follow vma/vta; vstart>=vl (including vl=0) leaves the destination unchanged. Success resets vstart=0.

VVector Operations

Related Search Terms

VSRL.VI instruction RISC-V VSRL.VI vsrl.vi syntax vsrl.vi encoding RVV logical shift right uimm shift count SEW shift count

Instruction Behavior

VSRL.VI performs RVV single-width integer logical right shift. Each active element reads vs2[i], takes the shift amount from uimm, uses only the low bits selected by SEW as specified by the V extension, and writes the result to vd. With vm=0, v0.t selects which body elements participate in this shift.

VSRL.VI Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VSRL takes the low shift-count bits, shifts active elements right logically, and fills high bits with zero.

Instruction input

vsrl.vi

vdUse v1-v31; v0 is the execution maskvs2Use v1-v31; v0 supplies the EEW=1 execution maskuimmUse 0..31vmexecution mask control

Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW, LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Equal-width source/destination overlap is legal; equal source registers require equal elements. With v0.t, vd/vs2/vs1 cannot be v0. Use low log2(SEW) shift-count bits and keep low SEW result bits; inactive/tail values are not specified here. VL=0 leaves the destination unchanged; stages are not processor cycles.

Execution Context

VLSEWvs2 elementscomma-separated

immediate value

4 -> shamt 4

5-bit unsigned uimm; shift count uses low lg2(SEW) bits

v0 mask bitscontinuous 0/1 bit string

OP-V encodingvsrl.vi

funct6

101000

vs2

01000

uimm

00100

funct3

011

00100

opcode

1010111

lane

0x00fa

0x010b

0x011c

0x012d

0x013e

0x014f

0x0160

0x0171

imm

0x0004

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vsrl.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the uimm field in one encoding strip.

This animation shows OP-V decode, low-bit shift-count selection, per-element right shifts, and destination writeback; it does not model pipelines or timing.

Quick Understanding & Search Notes

VSRL.VI applies logical right shift lane by lane to active elements within the current vl. The full shift source is not used as a count directly; the count uses only the low log2(SEW) bits, and mask-off or tail elements follow the current vtype policies.

VSRL uses OP-V vector-arithmetic encoding with funct6=101000; the .vi form is selected by funct3=011.

The VI form uses the 5-bit unsigned uimm field as the shift-count source. The actual count uses only the low log2(SEW) bits.

VSRL.VI shifts right logically and fills high bits with zero; it shifts the unsigned bit pattern right. Ordinary VSLL/VSRL/VSRA do not use vxrm rounding and do not set vxsat.

vm=0 uses the v0 mask and vm=1 is unmasked; mask-off body elements and tail elements follow the current mask/tail policy.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture

Vector Execution Context

V 1.0 requires enabled vector state, vill=0 and supported vtype/SEW. vd/vs2 are aligned EEW=SEW, EMUL=LMUL groups. uimm is zero-extended, 5-bit, 0–31; SEW=64 still cannot encode 32–63.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Bit Operations & Masks

Assume enabled V/VS, valid supported vtype, LMUL=m1, VLEN=4096, XLEN=64, vstart=0, initialized sources and all body mask bits enabled. SEW=8, vl=4, uimm=3, v12=[1,127,128,255] → v8=[0,15,16,31]. Inactive/tail follow vma/vta without guaranteed zeroing. Success resets vstart=0.

Vector Operations

Bitfield Ops

Pre-Use Checklist

Syntax Check

V 1.0 requires enabled vector state, vill=0 and supported vtype/SEW. vd/vs2 are aligned EEW=SEW, EMUL=LMUL groups. uimm is zero-extended, 5-bit, 0–31; SEW=64 still cannot encode 32–63.
32-bit OP-V: opcode=1010111, funct6=101000, funct3=011; vm at bit25, vs2 at bits24:20, uimm at bits19:15, vd at bits11:7. shamt uses only low lg2(SEW) bits. Logical right shift fills high bits with zero. No vxrm rounding or vxsat change.

Semantic Check

Optional v0.t means vm=0; omission means vm=1. Masked vd excludes v0; v0 cannot supply both EEW=1 mask and SEW data. Equal-width source/destination overlap is allowed. Compute active vstart<=i<vl only; prestart is unchanged, inactive/tail follow vma/vta; vstart>=vl (including vl=0) leaves the destination unchanged. Success resets vstart=0.

Pitfalls / Common Confusions

Do not treat the full VSRL.VI shift source as the shift count; the actual count uses only the low bits specified by SEW.

VSRL.VI is an ordinary integer shift; it does not use vxrm rounding and does not set vxsat because bits were shifted out.

A mask-off body element is not a deterministic zero write; the destination element follows the current mask policy.

FAQ

What shift counts can VSRL.VI encode?

uimm encodes only 0–31. The count uses low lg2(SEW) bits: 31 becomes 7 for SEW=8; SEW=64 still cannot encode 32–63.

How is VSRL.VI different from nearby shift instructions?

VSRL shifts right logically and fills high bits with zero; VSRA shifts right arithmetically and extends the signed element sign bit.