Does VSRL.VI set vxsat?
No. Ordinary shifts do not use the fixed-point saturation flag.
VSRL.VI
RISC-V VSRL.VI Instruction Details
Instruction ManualI-typeElement-wise logical right shift.
Instruction Syntax
vsrl.vi vd, vs2, uimm, vm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
VVector Operations
Related Search Terms
Instruction Behavior
VSRL.VI applies an element-wise logical right shift using the shift amount from uimm and writes vd.
Quick Understanding & Search Notes
VSRL.VI is a ordinary vector shift instruction; the shift amount uses only the architecturally specified low bits.
Ordinary VSLL/VSRL/VSRA do not use vxrm rounding.
Logical right shift shifts zeros into high bits.
VI/VV/VX forms take shift amounts from an immediate, vector elements, or a scalar register respectively.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsrl.vi v8, v12, 3, v0.t».
Data Storing
Understand this scenario with real code like «vsrl.vi v8, v12, 3, v0.t».
Vector Operations
Understand this scenario with real code like «vsrl.vi v8, v12, 3, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The shift amount comes from immediate; only the architecturally specified low bits are used.
Logical right shift shifts in zeros at the top.
Ordinary shifts do not use vxrm and do not set vxsat.