Can the VSLL.VX shift count exceed SEW?
The source value may exceed SEW, but only its low log2(SEW) bits are used, giving an effective count of 0..SEW-1.
VSLL.VX
RISC-V VSLL.VX Instruction Details
Instruction ManualOPIVXElement-wise logical left shift.
Instruction Syntax
vsll.vx vd, vs2, rs1, vm
Operand Breakdown
vd/vs2 are SEW/LMUL vector groups; rs1 is an integer shift-count register; x0 supplies zero. XLEN<SEW sign-extends the scalar.
32-bit OP-V: opcode=1010111, funct6=100101, funct3=100; vm at bit25, vs2 at bits24:20, rs1 at bits19:15, vd at bits11:7.
Active vd[i]=(vs2[i]<<shamt) mod 2^SEW; shamt uses only low log2(SEW) bits. Zero-fill low bits without rounding or saturation. Equal-width source/destination overlap is legal; masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data.
Optional v0.t means vm=0; omission means vm=1. Compute only enabled elements vstart≤i<vl; prestart stays unchanged, and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination. Examples assume SEW=16, LMUL=m1, vl=8, vstart=0 and initialized sources/masks.
Require V 1.0, enabled vector state and valid supported vtype/SEW; normal completion resets vstart=0. Animation stages are teaching steps, not processor cycles.
VVector Operations
Instruction Behavior
VSLL.VX computes vd[i]=(vs2[i]<<shamt) mod 2^SEW for active elements; shamt uses the low log2(SEW) bits of x[rs1]. With vm=0, v0.t selects body elements; inactive/tail follow vma/vta.
VSLL.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSLL takes the low shift-count bits, shifts active elements left, and writes the low SEW result.
Instruction input
vsll.vx
Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW, LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Equal-width source/destination overlap is legal; equal source registers require equal elements. With v0.t, vd/vs2/vs1 cannot be v0. Use low log2(SEW) shift-count bits and keep low SEW result bits; inactive/tail values are not specified here. VL=0 leaves the destination unchanged; stages are not processor cycles.
Execution Context
Shift-count rule: only the low lg2(SEW) bits of the x[rs1] value are used.
OP-V encodingvsll.vx
funct6
100101
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
<<
<<
<<
<<
<<
<<
<<
<<
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vsll.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows OP-V decode, low-bit shift-count selection, per-element logical left shift, and destination writeback; it does not model pipelines or timing.
Quick Understanding & Search Notes
Shift left, zero-fill low bits, and retain only SEW result bits. With vstart≥vl (including vl=0), the entire destination stays unchanged.
VSLL uses OP-V vector-arithmetic encoding with funct6=100101; the .vx form is selected by funct3=100.
The VX form takes the shift-count source from integer register x[rs1]. The actual count uses only the low log2(SEW) bits.
VSLL.VX shifts left and fills low bits with zero; it keeps the low SEW bits. Ordinary VSLL/VSRL/VSRA do not use vxrm rounding and do not set vxsat.
vm=0 uses the v0 mask and vm=1 is unmasked; mask-off body elements and tail elements follow the current mask/tail policy.
Equal-EEW sources/destination may overlap; masked vd cannot be v0, and v0 cannot supply both the EEW=1 mask and SEW source data.
Vector Execution Context
vd/vs2 are SEW/LMUL vector groups; rs1 is an integer shift-count register; x0 supplies zero. XLEN<SEW sign-extends the scalar.
32-bit OP-V: opcode=1010111, funct6=100101, funct3=100; vm at bit25, vs2 at bits24:20, rs1 at bits19:15, vd at bits11:7.
Active vd[i]=(vs2[i]<<shamt) mod 2^SEW; shamt uses only low log2(SEW) bits. Zero-fill low bits without rounding or saturation. Equal-width source/destination overlap is legal; masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data.
Optional v0.t means vm=0; omission means vm=1. Compute only enabled elements vstart≤i<vl; prestart stays unchanged, and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination. Examples assume SEW=16, LMUL=m1, vl=8, vstart=0 and initialized sources/masks.
Require V 1.0, enabled vector state and valid supported vtype/SEW; normal completion resets vstart=0. Animation stages are teaching steps, not processor cycles.
Common Usage Scenarios
Bit Operations & Masks
Assume enabled V/VS, valid supported m1, VLEN=4096, XLEN=64, vstart=0 and initialized sources with every body mask bit enabled. SEW=8, vl=4, x5=3, v12=[1,31,128,255] → v8=[8,248,0,248]. Inactive/tail follow vma/vta; success resets vstart=0.
Vector Operations
Assume enabled V/VS, valid supported m1, VLEN=4096, XLEN=64, vstart=0 and initialized sources with every body mask bit enabled. SEW=8, vl=4, x5=3, v12=[1,31,128,255] → v8=[8,248,0,248]. Inactive/tail follow vma/vta; success resets vstart=0.
Power-of-2 Multiply
Assume enabled V/VS, valid supported m1, VLEN=4096, XLEN=64, vstart=0 and initialized sources with every body mask bit enabled. SEW=8, vl=4, x5=3, v12=[1,31,128,255] → v8=[8,248,0,248]. Inactive/tail follow vma/vta; success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd/vs2 are SEW/LMUL vector groups; rs1 is an integer shift-count register; x0 supplies zero. XLEN<SEW sign-extends the scalar.
- 32-bit OP-V: opcode=1010111, funct6=100101, funct3=100; vm at bit25, vs2 at bits24:20, rs1 at bits19:15, vd at bits11:7.
Semantic Check
- Active vd[i]=(vs2[i]<<shamt) mod 2^SEW; shamt uses only low log2(SEW) bits. Zero-fill low bits without rounding or saturation. Equal-width source/destination overlap is legal; masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data.
- Optional v0.t means vm=0; omission means vm=1. Compute only enabled elements vstart≤i<vl; prestart stays unchanged, and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination. Examples assume SEW=16, LMUL=m1, vl=8, vstart=0 and initialized sources/masks.
- Require V 1.0, enabled vector state and valid supported vtype/SEW; normal completion resets vstart=0. Animation stages are teaching steps, not processor cycles.
Pitfalls / Common Confusions
Do not treat the full VSLL.VX shift source as the shift count; the actual count uses only the low bits specified by SEW.
VSLL.VX is an ordinary integer shift; it does not use vxrm rounding and does not set vxsat because bits were shifted out.
A mask-off body element is not a deterministic zero write; the destination element follows the current mask policy.
FAQ
How is VSLL.VX different from nearby shift instructions?
VSLL shifts left and fills low bits with zero; VSRL shifts right logically and fills high bits with zero; VSRA shifts right arithmetically and copies the signed element sign bit.