Does VSLL.VV set vxsat?
No. Ordinary shifts do not use the fixed-point saturation flag.
VSLL.VV
RISC-V VSLL.VV Instruction Details
Instruction ManualR-typeElement-wise logical left shift.
Instruction Syntax
vsll.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations
Related Search Terms
Instruction Behavior
VSLL.VV applies an element-wise logical left shift using the shift amount from vs1[i] and writes vd.
Quick Understanding & Search Notes
VSLL.VV is a ordinary vector shift instruction; the shift amount uses only the architecturally specified low bits.
Ordinary VSLL/VSRL/VSRA do not use vxrm rounding.
Left shift shifts zeros into low bits and keeps the SEW-width result.
VI/VV/VX forms take shift amounts from an immediate, vector elements, or a scalar register respectively.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsll.vv v8, v12, v4, v0.t».
Data Storing
Understand this scenario with real code like «vsll.vv v8, v12, v4, v0.t».
Vector Operations
Understand this scenario with real code like «vsll.vv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The shift amount comes from vs1[i]; only the architecturally specified low bits are used.
This is a logical left shift; high bits shifted out of SEW are discarded.
This instruction does not use vxrm and does not set vxsat.