How is VNCLIPU.WV different from VNSRL/VNSRA?
VNCLIPU.WV rounds shifted-out bits using vxrm and saturates with vxsat when the result is outside the unsigned SEW range; VNSRL/VNSRA are narrowing shifts without saturation clipping.
VNCLIPU.WV
RISC-V VNCLIPU.WV Instruction Details
Instruction ManualOPIVVVNCLIPU.WV is an RVV unsigned fixed-point narrowing clip instruction that rounds a 2*SEW source with vxrm and saturates to SEW.
Instruction Syntax
vnclipu.wv vd, vs2, vs1, vm
Operand Breakdown
vd is the SEW/LMUL narrow destination group; vs2 is the 2*SEW/2*LMUL wide source group. Group starts must align, EMUL≤8, and source/destination widths must be supported.
The count comes from the same-lane SEW-wide vs1 element; only its low lg2(2*SEW) bits are used. Interpret the source as unsigned, apply the vxrm rnu/rne/rdn/rod rounded right shift, then saturate to unsigned SEW; active saturation sets sticky vxsat.
vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. One register cannot supply sources at multiple EEWs.
vm denotes optional v0.t: vm=0 selects active body elements, omitted for vm=1. A masked vd cannot contain v0; v0 cannot supply both mask and data. Body satisfies vstart≤i<vl; vstart≥vl (including vl=0) updates no destination elements.
Require V 1.0, enabled vector state, and valid supported vtype. The example assumes LMUL=m1, SEW=8, vl=4, vstart=0, and initialized sources, vxrm, and v0.
VVector Fixed-PointNarrowing/Clip
Instruction Behavior
VNCLIPU.WV reads each active 2*SEW-wide vs2 element, performs a fixed-point rounded right shift using a shift amount from the same-lane vs1 element, then clips into the unsigned SEW range and writes the SEW-wide vd result; any active saturation sets sticky vxsat.
VNCLIPU.WV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VNCLIPU reads 2*SEW-wide vs2, rounded-shifts right using the shift amount and vxrm, saturates into a unsigned SEW-wide vd result, and sets vxsat on saturation.
Instruction input
vnclipu.wv
Require enabled vector state, valid vtype, and support for source 2*SEW and destination SEW; VL=0 updates no destination elements. Same-start narrow-destination/wide-source overlap is legal and forces mask- and tail-agnostic behavior. Only body elements are shown; no definite inactive or tail values are invented.
Execution Context
The teaching model fixes LMUL=m1, vstart=0, and VLEN=4096, so VLMAX=4096/16=256. Only body elements for selected VL=8 are shown; support for source 2*SEW and destination SEW is assumed. Wide vs2 has EMUL=2 and must start at an even register; .wv vs1 cannot overlap the wide source group. No definite inactive or tail results are shown; legal different-EEW overlap forces agnostic behavior. Steps are teaching stages, not processor cycles.
OP-V encodingvnclipu.wv
funct6
101110
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00000123
0x00001ff0
0x000000ff
0x7fffffff
0x00000100
0x00000007
0x00000123
0x00001ff0
clip>>
clip>>
clip>>
clip>>
clip>>
clip>>
clip>>
clip>>
v12
0x0001
0x0004
0x0000
0x0008
0x0002
0x0013
0x0001
0x0004
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
lane saturation
0
0
0
1
0
0
0
0
vxsat[0] is one sticky CSR bit: its prior value is 0, active lanes saturate in this instruction, and its state after writeback is 1. The lane-saturation row above only shows which lanes trigger this instruction's set condition.
Current step
Show OP-V 32-bit encoding fields
vnclipu.wv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW-to-SEW narrowing clip integer unsigned narrowing clip, vxrm fixed-point rounding, and vd writeback; this example sets sticky vxsat. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VNCLIPU.WV narrows a wide fixed-point intermediate back to SEW width: it applies a rounded right shift using the shift amount and vxrm, clips to the unsigned destination range, and records active-element saturation in vxsat.
The WV form uses OP-V encoding; funct6=101110, and funct3=000 selects the .wv operand form.
Source vs2 elements are interpreted at 2*SEW width and destination vd elements are SEW wide; the shift amount comes from the same-lane vs1 element.
Only the low lg2(2*SEW) bits of each vs1 shift amount control the actual shift.
Rounding is controlled by vxrm mode rnu, rne, rdn, or rod, followed by saturation into the unsigned destination range.
Only active elements with vstart≤i<vl and mask enabled compute; inactive/tail follow vma/vta and do not contribute to vxsat.
Require V, enabled vector state, valid vtype and supported source/destination widths; VL=0 updates no destination and does not newly set vxsat.
Vector Execution Context
vd is the SEW/LMUL narrow destination group; vs2 is the 2*SEW/2*LMUL wide source group. Group starts must align, EMUL≤8, and source/destination widths must be supported.
The count comes from the same-lane SEW-wide vs1 element; only its low lg2(2*SEW) bits are used. Interpret the source as unsigned, apply the vxrm rnu/rne/rdn/rod rounded right shift, then saturate to unsigned SEW; active saturation sets sticky vxsat.
vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. One register cannot supply sources at multiple EEWs.
vm denotes optional v0.t: vm=0 selects active body elements, omitted for vm=1. A masked vd cannot contain v0; v0 cannot supply both mask and data. Body satisfies vstart≤i<vl; vstart≥vl (including vl=0) updates no destination elements.
Require V 1.0, enabled vector state, and valid supported vtype. The example assumes LMUL=m1, SEW=8, vl=4, vstart=0, and initialized sources, vxrm, and v0.
Common Usage Scenarios
Fixed-point result narrowing
Assume enabled V/VS, valid m1, VLEN≥128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, vs2=[3,5,511,65535], vs1=[1,1,1,1], vxrm=rne, prior vxsat=0 → vd=[2,2,255,255], vxsat=1. This demonstrates unsigned saturation after rounding. Inactive/tail values follow policy without assumed zeroing.
Fixed-point scaled and rounded output
Assume enabled V/VS, valid m1, VLEN≥128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, vs2=[3,5,511,65535], vs1=[1,1,1,1], vxrm=rne, prior vxsat=0 → vd=[2,2,255,255], vxsat=1. This demonstrates unsigned saturation after rounding. Inactive/tail values follow policy without assumed zeroing.
Wide-to-narrow conversion that needs a saturation flag
Assume enabled V/VS, valid m1, VLEN≥128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, vs2=[3,5,511,65535], vs1=[1,1,1,1], vxrm=rne, prior vxsat=0 → vd=[2,2,255,255], vxsat=1. This demonstrates unsigned saturation after rounding. Inactive/tail values follow policy without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd is the SEW/LMUL narrow destination group; vs2 is the 2*SEW/2*LMUL wide source group. Group starts must align, EMUL≤8, and source/destination widths must be supported.
- The count comes from the same-lane SEW-wide vs1 element; only its low lg2(2*SEW) bits are used. Interpret the source as unsigned, apply the vxrm rnu/rne/rdn/rod rounded right shift, then saturate to unsigned SEW; active saturation sets sticky vxsat.
Semantic Check
- vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. One register cannot supply sources at multiple EEWs.
- vm denotes optional v0.t: vm=0 selects active body elements, omitted for vm=1. A masked vd cannot contain v0; v0 cannot supply both mask and data. Body satisfies vstart≤i<vl; vstart≥vl (including vl=0) updates no destination elements.
- Require V 1.0, enabled vector state, and valid supported vtype. The example assumes LMUL=m1, SEW=8, vl=4, vstart=0, and initialized sources, vxrm, and v0.
Pitfalls / Common Confusions
VNCLIPU.WV uses 2*SEW-wide vs2 elements and writes SEW-wide vd results; do not read it as an ordinary single-width shift.
Rounding comes from the V extension fixed-point CSR vxrm, not floating-point frm.
VNCLIPU clips into the unsigned range; sticky vxsat is set only when an active element saturates.
FAQ
When does VNCLIPU.WV set vxsat?
This instruction sets sticky vxsat when any active element has a rounded shifted result outside the unsigned SEW range and is clipped. Elements disabled by v0.t do not participate in that decision.