How is VSMUL.VV different from VMUL/VMULH?
VMUL/VMULH are ordinary integer multiply low-half or high-half operations; VSMUL is signed fixed-point fractional multiply, scales by SEW-1 bits, rounds with vxrm, and can set vxsat.
VSMUL.VV
RISC-V VSMUL.VV Instruction Details
Instruction ManualOPIVVVSMUL.VV is an RVV signed fixed-point fractional multiply instruction that uses vxrm rounding and sets vxsat on saturation.
Instruction Syntax
vsmul.vv vd, vs2, vs1, vm
Operand Breakdown
V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
Sources/destination: EEW=SEW, EMUL=LMUL. Equal-width overlap is allowed; masked vd and SEW sources exclude v0. Inactive/tail follow vma/vta: retain or all ones. VL=0 leaves vd and vxsat unchanged.
Shift the signed product right by SEW-1 with vxrm rounding, then saturate to SEW. Saturation sets vxsat; otherwise its prior value remains.
VVector OperationsFixed-Point Arithmetic
Instruction Behavior
VSMUL.VV reads each active vs2 element and the same-lane vs1 element, computes a 2*SEW signed product, rounds the value scaled right by SEW-1 bits according to vxrm, then saturates into the signed SEW range and writes vd; any active saturation sets sticky vxsat.
VSMUL.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSMUL forms a signed fractional 2*SEW product, rounds the SEW-1 scaled result with vxrm, saturates into vd, and sets vxsat on saturation.
Instruction input
vsmul.vv
Teaching context: V 1.0, enabled vector state, and valid supported vtype/SEW; fix LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Equal-width sources/destination may overlap; equal sources require equal elements. With v0.t, vd/vs2/vs1 exclude v0. Enter unsigned SEW bit patterns, interpreted as signed for multiplication. .vx takes low bits when XLEN>SEW and sign-extends when XLEN<SEW; x0 supplies zero. Only body is shown; inactive/tail follow vma/vta, retaining old values or becoming all ones, without definite displayed values. VL=0 leaves vd and vxsat unchanged; success resets vstart=0. Stages are teaching steps, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvsmul.vv
funct6
100111
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x8000
0x6000
0x4000
0x9000
0x2000
0x1000
0x8000
0x6000
frac*
frac*
frac*
frac*
frac*
frac*
frac*
frac*
v12
0x8000
0x6000
0x4000
0x2000
0x8000
0x3000
0x8000
0x6000
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
lane saturation
1
0
0
0
0
0
1
0
vxsat[0] is one sticky CSR bit: its prior value is 0, active lanes saturate in this instruction, and its state after writeback is 1. The lane-saturation row above only shows which lanes trigger this instruction's set condition.
Current step
Show OP-V 32-bit encoding fields
vsmul.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed fractional saturating multiply, vxrm fixed-point rounding, and vd writeback; this example sets sticky vxsat. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VSMUL.VV multiplies two signed SEW fixed-point fractions, equivalent to scaling the 2*SEW product by SEW-1 bits, rounding with vxrm, and signed saturation; it is Q-format-style fractional multiply, not ordinary integer multiply.
32-bit OP-V: opcode=1010111, funct6=100111, funct3=000 (OPIVV).
Active vd[i]=clip(roundoff_signed(vs2[i]*vs1[i], SEW-1)); vxrm selects rnu/rne/rdn/rod.
With SEW=8, -128*-128 shifted right 7 gives 128, saturating to 127 and setting vxsat=1; no saturation leaves prior vxsat set.
Active elements have vstart<=i<vl and enabled mask. v0.t means vm=0; omission means vm=1. Masked vd and SEW data sources exclude v0.
Source/destination EEW=SEW, EMUL=LMUL; register groups align and equal-width overlap is allowed. Prestart is unchanged; inactive/tail follow vma/vta, retaining old values or becoming all ones. vstart>=vl, including VL=0, leaves vd and vxsat unchanged. Success resets vstart=0.
V 1.0 requires enabled vector state, vill=0 and supported vtype/SEW/LMUL; virtualization V=1 also requires non-Off vsstatus.VS.
Vector Execution Context
V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
Sources/destination: EEW=SEW, EMUL=LMUL. Equal-width overlap is allowed; masked vd and SEW sources exclude v0. Inactive/tail follow vma/vta: retain or all ones. VL=0 leaves vd and vxsat unchanged.
Shift the signed product right by SEW-1 with vxrm rounding, then saturate to SEW. Saturation sets vxsat; otherwise its prior value remains.
Common Usage Scenarios
Signed fixed-point fractional multiplication
Understand this scenario with real code like «vsmul.vv v4, v8, v12, v0.t # signed fractional multiply, vxrm rounding, vxsat on saturation».
Vector scaling with vxrm rounding
Understand this scenario with real code like «vsmul.vv v4, v8, v12, v0.t # signed fractional multiply, vxrm rounding, vxsat on saturation».
Detecting saturation through vxsat
Understand this scenario with real code like «vsmul.vv v4, v8, v12, v0.t # signed fractional multiply, vxrm rounding, vxsat on saturation».
Pre-Use Checklist
Syntax Check
- V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
- Sources/destination: EEW=SEW, EMUL=LMUL. Equal-width overlap is allowed; masked vd and SEW sources exclude v0. Inactive/tail follow vma/vta: retain or all ones. VL=0 leaves vd and vxsat unchanged.
Semantic Check
- Shift the signed product right by SEW-1 with vxrm rounding, then saturate to SEW. Saturation sets vxsat; otherwise its prior value remains.
Pitfalls / Common Confusions
VSMUL is signed fractional multiply: the product is scaled by SEW-1 bits and rounded by vxrm, not truncated like VMUL low-half.
Saturation occurs only when the rounded value is outside the signed SEW range; saturation sets sticky vxsat.
vm/v0.t only controls which body elements execute; masked-off elements do not participate in this instruction's saturation decision.
FAQ
When does VSMUL set vxsat?
Any active rounded result outside the signed SEW range saturates and sets vxsat. Otherwise vxsat retains its prior value; masked-off elements cannot set it.