Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSMUL.VV
RISC-V VSMUL.VV Instruction Details
Instruction ManualOPIVVVSMUL.VV is an RVV signed fixed-point fractional multiply instruction that uses vxrm rounding and sets vxsat on saturation.
Instruction Syntax
vsmul.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsFixed-Point Arithmetic
Instruction Behavior
VSMUL.VV reads each active vs2 element and the same-lane vs1 element, computes a 2*SEW signed product, rounds the value scaled right by SEW-1 bits according to vxrm, then saturates into the signed SEW range and writes vd; any active saturation sets sticky vxsat.
VSMUL.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSMUL forms a signed fractional 2*SEW product, rounds the SEW-1 scaled result with vxrm, saturates into vd, and sets vxsat on saturation.
Instruction input
vsmul.vv
OP-V encodingvsmul.vv
funct6
100111
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x8000
0x6000
0x4000
0x9000
0x2000
0x1000
0x8000
0x6000
frac*
frac*
frac*
frac*
frac*
frac*
frac*
frac*
v12
0x8000
0x6000
0x4000
0x2000
0x8000
0x3000
0x8000
0x6000
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
vxsat
1
0
0
0
0
0
1
0
Current step
Show OP-V 32-bit encoding fields
vsmul.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed fractional saturating multiply, vxrm fixed-point rounding, and vd writeback; this example sets sticky vxsat. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VSMUL.VV multiplies two signed SEW fixed-point fractions, equivalent to scaling the 2*SEW product by SEW-1 bits, rounding with vxrm, and signed saturation; it is Q-format-style fractional multiply, not ordinary integer multiply.
The VV form uses OP-V encoding; funct6=100111, and funct3=000 selects the .vv operand form.
Source operands are interpreted as signed two's-complement fixed-point fractions, with the second source from the same-lane vs1 element.
The rounding mode comes from the V extension fixed-point rounding-mode CSR vxrm: rnu, rne, rdn, or rod.
The result saturates into the signed SEW range; saturation in any active element sets sticky vxsat.
VSMUL does not set floating-point exception flags and does not use floating-point frm rounding.
Vector Execution Context
When reading VSMUL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Fixed-point DSP fractional multiply
Understand this scenario with real code like «vsmul.vv v4, v8, v12, v0.t # signed fractional multiply, vxrm rounding, vxsat on saturation».
Audio and signal-processing kernels
Understand this scenario with real code like «vsmul.vv v4, v8, v12, v0.t # signed fractional multiply, vxrm rounding, vxsat on saturation».
Vector fixed-point code that needs a saturation flag
Understand this scenario with real code like «vsmul.vv v4, v8, v12, v0.t # signed fractional multiply, vxrm rounding, vxsat on saturation».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVV.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
VSMUL is signed fractional multiply: the product is scaled by SEW-1 bits and rounded by vxrm, not truncated like VMUL low-half.
Saturation occurs only when the rounded value is outside the signed SEW range; saturation sets sticky vxsat.
vm/v0.t only controls which body elements execute; masked-off elements do not participate in this instruction's saturation decision.
FAQ
How is VSMUL.VV different from VMUL/VMULH?
VMUL/VMULH are ordinary integer multiply low-half or high-half operations; VSMUL is signed fixed-point fractional multiply, scales by SEW-1 bits, rounds with vxrm, and can set vxsat.
When does VSMUL set vxsat?
VSMUL sets sticky vxsat when any active element has a rounded scaled result outside the signed SEW range and saturates. Elements disabled by v0.t do not participate in this instruction's saturation decision.