How does VMUL.VV handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.
VMUL.VV
RISC-V VMUL.VV Instruction Details
Instruction ManualR-typeMultiply elements and return the low SEW bits of each product.
Instruction Syntax
vmul.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector IntegerMultiply
Instruction Behavior
VMUL.VV is a RISC-V V integer multiply instruction. It returns the low SEW bits of the 2*SEW product; the low half is the same for signed and unsigned multiplication. Results are written to active vd elements.
Quick Understanding & Search Notes
VMUL.VV writes only active elements; integer overflow keeps the low SEW bits and does not trap.
Vector-scalar .vx forms use x[rs1], while vector-vector .vv forms use vs1.
Results are written at SEW width; high-half multiply explicitly returns the high SEW bits of the 2*SEW product.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Common Usage Scenarios
General Multiply
Understand this scenario with real code like «vmul.vv v8, v4, v6».
Fixed-Point
Understand this scenario with real code like «vmul.vv v8, v4, v6».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only SEW bits (like C overflow truncation)
Not widening; use vwmul