Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMUL.VV
RISC-V VMUL.VV Instruction Details
Instruction ManualR-typeVMUL.VV forms each active element's 2*SEW integer product and writes the product's low SEW bits.
Instruction Syntax
vmul.vv vd, vs2, vs1, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector IntegerMultiply
Instruction Behavior
VMUL.VV is a RISC-V V extension single-width integer vector-vector multiply instruction. Each active element reads vs2 and the second source from vector register vs1, forms a 2*SEW product, and writes the low SEW bits to vd. The low half is independent of signedness; with vm=0, only body elements whose v0.t bit is 1 are processed, while masked-off and tail elements follow the current vtype policies.
VMUL.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMUL forms a 2*SEW product and writes the low SEW bits to vd.
Instruction input
vmul.vv
OP-V encodingvmul.vv
funct6
100101
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xfffe
0x003a
0x004f
0xfffb
0x0079
0x008e
0xfff8
0x00b8
*
*
*
*
*
*
*
*
v12
0x0009
0xfffb
0x001f
0xfff9
0x0035
0xfff7
0x004b
0xfff5
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vmul.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer low-half multiplication, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMUL.VV does not write a full widening product. It forms a 2*SEW product for active elements within the current vl and writes only the low SEW bits to vd; the second source comes from vector register vs1, and the low half is independent of signedness.
VMUL.VV uses OP-V multiply-class encoding; the .vv form is selected by funct3=010, and funct6=100101 selects VMUL.
Each active element first forms a 2*SEW product and then writes the low SEW bits; vd remains an SEW-width ordinary vector destination, not a 2*SEW widening destination.
The second source comes from the same-lane element of vs1; this instruction is not a reduction and does not combine lanes.
The low half is independent of signedness.
Only body elements within the current vl are processed; vm=0 uses the v0.t mask, and masked-off plus tail elements follow the current vtype policies.
Vector Execution Context
When reading VMUL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
General Multiply
Understand this scenario with real code like «vmul.vv v4, v8, v12, v0.t # low SEW bits of v8[i] * v12[i]».
Fixed-Point
Understand this scenario with real code like «vmul.vv v4, v8, v12, v0.t # low SEW bits of v8[i] * v12[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
VMUL writes only the low SEW bits, not the full 2*SEW product; use VWMUL* when a full widening result is required.
The low half is the same for signed and unsigned multiplication, but high-half results require VMULH, VMULHU, or VMULHSU.
With vm=0, v0.t is the execution mask; the destination value for masked-off elements is controlled by the current vtype.vma policy.
These instructions are not multiply-accumulate operations and do not read old vd as an accumulator; use VMACC/VWMACC-family instructions for accumulation.
FAQ
How does VMUL.VV differ from VWMUL*?
VMUL.VV writes only the low SEW bits to an SEW-width vd. VWMUL* writes the full 2*SEW widening product.
Does VMUL.VV read old vd for accumulation?
No. This instruction writes only the selected low SEW bits from the current multiply; use VMACC/VWMACC-family multiply-accumulate instructions when accumulation is required.