Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWMUL.VV
RISC-V VWMUL.VV Instruction Details
Instruction ManualR-typeVWMUL.VV produces full 2*SEW widening products for active elements and does not accumulate old vd.
Instruction Syntax
vwmul.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsInteger Arithmetic
Instruction Behavior
VWMUL.VV is a RISC-V V extension signed widening vector multiply instruction. Each active element interprets the two SEW-width sources as signed vs2[i] and signed vs1[i], computes the full 2*SEW product, and writes vd. With vm=0, only body elements whose v0.t bit is 1 execute the multiply; masked-off and tail elements follow the current vtype policies.
VWMUL.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWMUL interprets SEW source elements as signed-by-signed and writes the full 2*SEW product to vd.
Instruction input
vwmul.vv
OP-V encodingvwmul.vv
funct6
111011
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xfff0
0x0032
0x0043
0xffed
0x0065
0x0076
0xffea
0x0098
w*
w*
w*
w*
w*
w*
w*
w*
v12
0x0005
0xfff7
0x0017
0xfff5
0x0029
0xfff3
0x003b
0xfff1
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwmul.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer signed widening multiplication, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWMUL.VV multiplies two SEW-width sources and writes the full 2*SEW product. It processes only active elements within the current vl, the second source comes from vector register vs1, and the signedness is signed vs2[i] and signed vs1[i].
VWMUL.VV uses OP-V multiply-class encoding; the .vv form is selected by funct3=010.
Each active element performs vd[i] = sign_extend(vs2[i]) * sign_extend(vs1[i]), producing a 2*SEW-wide result written to widening destination vd.
The destination register group EMUL is twice the source EMUL and must satisfy the V extension legality requirements for widening destinations.
Only body elements within the current vl are processed; vm=0 uses the v0.t mask, and masked-off plus tail elements follow the current vtype policies.
This instruction is not multiply-accumulate and does not read old vd; use the matching VWMACC* instruction when accumulation is required.
Vector Execution Context
When reading VWMUL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vectorized Loops
Understand this scenario with real code like «vwmul.vv v8, v4, v12, v0.t # signed widening product».
Integer Multiply
Understand this scenario with real code like «vwmul.vv v8, v4, v12, v0.t # signed widening product».
Multi-Precision Arithmetic
Understand this scenario with real code like «vwmul.vv v8, v4, v12, v0.t # signed widening product».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The result width is 2*SEW and destination EMUL is twice the source EMUL; this differs from single-width VMUL/VMULH.
VWMUL* writes only the product and does not read old vd as an accumulator; use VWMACC* for widening multiply-accumulate.
VWMUL.VV uses signed vs2[i] and signed vs1[i] interpretation; do not confuse it with the other VWMUL, VWMULU, and VWMULSU forms.
With vm=0, masked-off destination elements follow the current mask policy; do not assume fixed zeroing or preserving.
FAQ
How does VWMUL.VV differ from VMUL or VMULH?
VWMUL.VV writes the full 2*SEW widening product. VMUL writes the low SEW bits, while VMULH-family instructions write the high SEW bits.
Does VWMUL.VV read old vd for accumulation?
No. VWMUL.VV writes only the product; widening multiply-accumulate semantics belong to VWMACC* instructions.