Do inactive, tail and prestart elements behave identically?
Prestart stays unchanged. Inactive/tail follow vma/vta: undisturbed, or agnostic (old values or all ones, without a fixed guarantee). Legal different-EEW overlap forces agnostic behavior.
VWMUL.VX
RISC-V VWMUL.VX Instruction Details
Instruction ManualV-typeVWMUL.VX writes the full signed 2*SEW product to vd without accumulation.
Instruction Syntax
vwmul.vx vd, vs2, rs1, vm
Operand Breakdown
RV32/RV64 V 1.0; enabled vector state, vill=0, supported SEW and 2*SEW. vd is a wide destination with EEW=2*SEW, EMUL=2*LMUL<=8 and an aligned group start. SEW=64 needs additional 128-bit integer elements.
32-bit OP-V: opcode=1010111, funct6=111011, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1/rs1. Optional v0.t means vm=0; omission means vm=1.
Form the full 2*SEW product as signed × signed and write vd directly. A narrow source overlaps wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. First take low scalar bits for XLEN>SEW or sign-extend for XLEN<SEW; x0 supplies zero.
Compute only mask-enabled vstart<=i<vl elements. Prestart stays unchanged; inactive/tail follow vma/vta: undisturbed or agnostic (old values or all ones). Masked vd excludes v0, which cannot supply mask and data together. vstart>=vl (including vl=0) leaves all destination elements unchanged; success resets vstart=0 without saturation or vxsat change.
VVector OperationsInteger Arithmetic
Instruction Behavior
RISC-V V 1.0 widening integer multiply using signed multiplicands. Write the full 2*SEW product. Require enabled vector state, valid vtype and supported SEW/2*SEW. Update only mask-enabled vstart<=i<vl elements; prestart stays unchanged. Inactive/tail follow vma/vta; legal different-EEW overlap forces agnostic behavior.
VWMUL.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWMUL interprets SEW source elements as signed-by-signed and writes the full 2*SEW product to vd.
Instruction input
vwmul.vx
Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096, vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements. Enter nonnegative SEW bit patterns, interpreted as signed two’s-complement. .vx takes low bits when XLEN>SEW or sign-extends when XLEN<SEW; x0 supplies zero. Write the full product to 2*SEW vd without accumulating old vd, saturation or vxsat change. Destination EMUL=2 requires an even start; a narrow source may overlap only its highest register, forcing mask/tail-agnostic behavior. Equal sources require equal initial values; with v0.t, vd and data sources exclude v0. Only body is shown, without definite inactive/tail values. VL=0 updates nothing; success resets vstart=0. Stages are not processor cycles.
Execution Context
OP-V encodingvwmul.vx
funct6
111011
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xfff0
0x0032
0x0043
0xffed
0x0065
0x0076
0xffea
0x0098
w*
w*
w*
w*
w*
w*
w*
w*
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwmul.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer signed widening multiplication, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWMUL.VX writes the full signed 2*SEW product to vd without accumulation.
Multiplicands: signed multiplicands; write only the full product, without old-vd accumulation.
Integer .vx takes low SEW bits for XLEN>SEW and sign-extends for XLEN<SEW, including unsigned interpretation; x0 supplies zero.
VL=0 or vstart>=vl leaves all destination elements unchanged; success resets vstart=0. No saturation or vxsat change.
Vector Execution Context
RV32/RV64 V 1.0; enabled vector state, vill=0, supported SEW and 2*SEW. vd is a wide destination with EEW=2*SEW, EMUL=2*LMUL<=8 and an aligned group start. SEW=64 needs additional 128-bit integer elements.
32-bit OP-V: opcode=1010111, funct6=111011, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1/rs1. Optional v0.t means vm=0; omission means vm=1.
Form the full 2*SEW product as signed × signed and write vd directly. A narrow source overlaps wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. First take low scalar bits for XLEN>SEW or sign-extend for XLEN<SEW; x0 supplies zero.
Compute only mask-enabled vstart<=i<vl elements. Prestart stays unchanged; inactive/tail follow vma/vta: undisturbed or agnostic (old values or all ones). Masked vd excludes v0, which cannot supply mask and data together. vstart>=vl (including vl=0) leaves all destination elements unchanged; success resets vstart=0 without saturation or vxsat change.
Common Usage Scenarios
Widening integer multiplication
Assume enabled V/VS, valid e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; v12=[255,128,1,127], x5=255. v8=[0x0001,0x0080,unchanged,0xff81], with 16-bit results. Lane2 and tails keep old values; vxsat is unchanged, and success resets vstart=0.
Pre-Use Checklist
Syntax Check
- RV32/RV64 V 1.0; enabled vector state, vill=0, supported SEW and 2*SEW. vd is a wide destination with EEW=2*SEW, EMUL=2*LMUL<=8 and an aligned group start. SEW=64 needs additional 128-bit integer elements.
- 32-bit OP-V: opcode=1010111, funct6=111011, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1/rs1. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Form the full 2*SEW product as signed × signed and write vd directly. A narrow source overlaps wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. First take low scalar bits for XLEN>SEW or sign-extend for XLEN<SEW; x0 supplies zero.
- Compute only mask-enabled vstart<=i<vl elements. Prestart stays unchanged; inactive/tail follow vma/vta: undisturbed or agnostic (old values or all ones). Masked vd excludes v0, which cannot supply mask and data together. vstart>=vl (including vl=0) leaves all destination elements unchanged; success resets vstart=0 without saturation or vxsat change.
Pitfalls / Common Confusions
Wide vd has EEW=2*SEW and EMUL=2*LMUL<=8; group starts align to EMUL.
A narrow source may overlap wide vd only with source EMUL>=1 and equal highest registers; mask/tail-agnostic behavior is then forced.
v0.t means vm=0; omission means vm=1. Masked vd excludes v0, which cannot supply mask and data together.
FAQ
Is SEW=64 always usable?
This widening operation needs implementation support for 128-bit integer elements, beyond baseline V guarantees. Check supported SEW/2*SEW and legal register groups.