Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWMULU.VX
RISC-V VWMULU.VX Instruction Details
Instruction ManualR-typeVWMULU.VX produces full 2*SEW widening products for active elements and does not accumulate old vd.
Instruction Syntax
vwmulu.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsInteger Arithmetic
Instruction Behavior
VWMULU.VX is a RISC-V V extension unsigned widening vector-scalar multiply instruction. Each active element interprets vs2 and x[rs1] after the official .vx scalar conversion as unsigned vs2[i] and unsigned x[rs1], computes the full 2*SEW product, and writes vd. With vm=0, only body elements whose v0.t bit is 1 execute the multiply; masked-off and tail elements follow the current vtype policies.
VWMULU.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWMULU interprets SEW source elements as unsigned-by-unsigned and writes the full 2*SEW product to vd.
Instruction input
vwmulu.vx
OP-V encodingvwmulu.vx
funct6
111000
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xfffe
0x003a
0x004f
0xfffb
0x0079
0x008e
0xfff8
0x00b8
w*
w*
w*
w*
w*
w*
w*
w*
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwmulu.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening multiplication, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWMULU.VX multiplies two SEW-width sources and writes the full 2*SEW product. It processes only active elements within the current vl, the second source comes from integer scalar register rs1 after the official .vx scalar conversion to SEW, and the signedness is unsigned vs2[i] and unsigned x[rs1].
VWMULU.VX uses OP-V multiply-class encoding; the .vx form is selected by funct3=110.
Each active element performs vd[i] = unsigned(vs2[i]) * unsigned(sew_scalar(x[rs1])), producing a 2*SEW-wide result written to widening destination vd. Here sew_scalar(x[rs1]) means the official .vx scalar rule: if XLEN>SEW, use the least-significant SEW bits of x[rs1]; if XLEN<SEW, sign-extend x[rs1] to SEW.
The destination register group EMUL is twice the source EMUL and must satisfy the V extension legality requirements for widening destinations.
Only body elements within the current vl are processed; vm=0 uses the v0.t mask, and masked-off plus tail elements follow the current vtype policies.
This instruction is not multiply-accumulate and does not read old vd; use the matching VWMACC* instruction when accumulation is required.
Vector Execution Context
When reading VWMULU.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vectorized Loops
Understand this scenario with real code like «vwmulu.vx v8, v12, x5, v0.t # unsigned scalar widening product».
Integer Multiply
Understand this scenario with real code like «vwmulu.vx v8, v12, x5, v0.t # unsigned scalar widening product».
Multi-Precision Arithmetic
Understand this scenario with real code like «vwmulu.vx v8, v12, x5, v0.t # unsigned scalar widening product».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The result width is 2*SEW and destination EMUL is twice the source EMUL; this differs from single-width VMUL/VMULH.
VWMUL* writes only the product and does not read old vd as an accumulator; use VWMACC* for widening multiply-accumulate.
VWMULU.VX uses unsigned vs2[i] and unsigned x[rs1] interpretation; do not confuse it with the other VWMUL, VWMULU, and VWMULSU forms.
With vm=0, masked-off destination elements follow the current mask policy; do not assume fixed zeroing or preserving.
FAQ
How does VWMULU.VX differ from VMUL or VMULH?
VWMULU.VX writes the full 2*SEW widening product. VMUL writes the low SEW bits, while VMULH-family instructions write the high SEW bits.
Does VWMULU.VX read old vd for accumulation?
No. VWMULU.VX writes only the product; widening multiply-accumulate semantics belong to VWMACC* instructions.