Which elements compute?
Only mask-enabled elements with vstart≤i<vl compute. When vstart≥vl (including vl=0), no destination elements are updated.
VWMACC.VX
RISC-V VWMACC.VX Instruction Details
Instruction ManualV-typevd[i] = old vd[i] + signed(x[rs1]) * signed(vs2[i]); keep low 2*SEW bits.
Instruction Syntax
vwmacc.vx vd, rs1, vs2, vm
Operand Breakdown
vd is a read/write accumulator with EEW=2*SEW and EMUL=2*LMUL<=8; vs2 and the converted rs1 scalar are SEW-bit multiplicands. Take low bits for XLEN>SEW or sign-extend for XLEN<SEW; x0 supplies zero.
32-bit OP-V: opcode=1010111, funct6=111101, funct3=110 (OPMVX); vm at bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Active vd[i]=(old vd[i]+signed(converted scalar)*signed(vs2[i])) mod 2^(2*SEW). Add the full product without saturation or vxsat change. Group starts align to EMUL; narrow multiplicands cannot overlap the wide vd accumulator source, which would read one register at different EEWs.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported SEW/2*SEW. Only mask-enabled vstart<=i<vl elements compute; prestart is unchanged and inactive/tail follow vma/vta. Masked vd excludes v0, which cannot supply mask and data together. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.
VVector OperationsInteger Arithmetic
Related Search Terms
Instruction Behavior
V 1.0: add the full signed rs1 scalar × signed vs2 product to old 2*SEW vd. Only active elements compute; no saturation.
VWMACC.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWMACC reads old 2*SEW vd as the accumulator, forms a signed-by-signed product, and writes the accumulated result.
Instruction input
vwmacc.vx
Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096, vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements. Enter nonnegative bit patterns; interpret both multiplicands as signed two’s-complement. Read old 2*SEW vd, add the full product, and keep low 2*SEW bits; no saturation or vxsat change. Scalars first follow XLEN/SEW conversion (sign-extend if narrower, take low bits if wider); x0 supplies zero. Wide vd is an EMUL=2 accumulator source with an even start and cannot overlap narrow multiplicands; equal narrow sources require equal initial values. With v0.t, vd and data sources exclude v0. Only body is shown; inactive/tail follow vma/vta without definite displayed values. VL=0 updates nothing; success resets vstart=0. Stages are not processor cycles.
Execution Context
OP-V encodingvwmacc.vx
funct6
111101
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0xffffffdf
0x00000131
0x00000162
0x00000193
0xffffffcb
0x000001f5
0x00000226
0x00000257
v8
0xfff0
0x0032
0x0043
0xffed
0x0065
0x0076
0xffea
0x0098
acc+w*
acc+w*
acc+w*
acc+w*
acc+w*
acc+w*
acc+w*
acc+w*
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwmacc.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer signed widening multiply-accumulate, old vd accumulator, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
Read old vd, add the full product, then write the low 2*SEW bits.
Require valid supported vtype, SEW and 2*SEW, with vector state enabled.
vd has EEW=2*SEW and EMUL=2*LMUL≤8; narrow multiplicands cannot overlap the wide accumulator source.
vm=0 uses v0.t; omitting the mask means vm=1. Prestart is unchanged; inactive/tail follow vma/vta.
Vector Execution Context
vd is a read/write accumulator with EEW=2*SEW and EMUL=2*LMUL<=8; vs2 and the converted rs1 scalar are SEW-bit multiplicands. Take low bits for XLEN>SEW or sign-extend for XLEN<SEW; x0 supplies zero.
32-bit OP-V: opcode=1010111, funct6=111101, funct3=110 (OPMVX); vm at bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Active vd[i]=(old vd[i]+signed(converted scalar)*signed(vs2[i])) mod 2^(2*SEW). Add the full product without saturation or vxsat change. Group starts align to EMUL; narrow multiplicands cannot overlap the wide vd accumulator source, which would read one register at different EEWs.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported SEW/2*SEW. Only mask-enabled vstart<=i<vl elements compute; prestart is unchanged and inactive/tail follow vma/vta. Masked vd excludes v0, which cannot supply mask and data together. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.
Common Usage Scenarios
Widening MAC
Assume enabled V/VS, valid e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; old v8=[1,1,1,1], v12=[255,128,1,127], x5=255. v8=[0x0002,0x0081,unchanged,0xff82], keeping low 16 bits. Lane2 and tails keep old values; vxsat is unchanged, and success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd is a read/write accumulator with EEW=2*SEW and EMUL=2*LMUL<=8; vs2 and the converted rs1 scalar are SEW-bit multiplicands. Take low bits for XLEN>SEW or sign-extend for XLEN<SEW; x0 supplies zero.
- 32-bit OP-V: opcode=1010111, funct6=111101, funct3=110 (OPMVX); vm at bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Active vd[i]=(old vd[i]+signed(converted scalar)*signed(vs2[i])) mod 2^(2*SEW). Add the full product without saturation or vxsat change. Group starts align to EMUL; narrow multiplicands cannot overlap the wide vd accumulator source, which would read one register at different EEWs.
- Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported SEW/2*SEW. Only mask-enabled vstart<=i<vl elements compute; prestart is unchanged and inactive/tail follow vma/vta. Masked vd excludes v0, which cannot supply mask and data together. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.
Pitfalls / Common Confusions
vd is a read/write accumulator, not a write-only product destination.
Old vd is a 2*SEW source; narrow multiplicands cannot read any register in that wide source group.