How does VWMULSU.VV differ from VMUL or VMULH?
VWMULSU.VV writes the full 2*SEW widening product. VMUL writes the low SEW bits, while VMULH-family instructions write the high SEW bits.
VWMULSU.VV
RISC-V VWMULSU.VV Instruction Details
Instruction ManualOPMVVVWMULSU.VV produces full 2*SEW widening products for active elements and does not accumulate old vd.
Instruction Syntax
vwmulsu.vv vd, vs2, vs1, vm
Operand Breakdown
vd is a wide destination with EEW=2*SEW and EMUL=2*LMUL<=8, aligned to EMUL; vs2 and vs1 supply SEW-bit multiplicands.
32-bit OP-V: opcode=1010111, funct6=111010, funct3=010 (OPMVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1. Optional v0.t means vm=0; omission means vm=1.
Multiply signed two’s-complement vs2 by the unsigned second source and write the full 2*SEW product without accumulating old vd. Equal sources use equal initial values. Only mask-enabled vstart<=i<vl elements update; vstart>=vl (including vl=0) leaves vd unchanged.
A narrow source overlaps wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Masked vd excludes v0, which cannot supply both mask and data. Prestart stays unchanged; vma/vta govern inactive/tail preservation or permitted all ones.
RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. Success resets vstart=0 without saturation or vxsat change. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
VVector OperationsInteger Arithmetic
Instruction Behavior
VWMULSU.VV is a RISC-V V extension signed-by-unsigned widening vector multiply instruction. Each active element interprets the two SEW-width sources as signed vs2[i] and unsigned vs1[i], computes the full 2*SEW product, and writes vd. With vm=0, only body elements whose v0.t bit is 1 execute the multiply; masked-off and tail elements follow the current vtype policies.
VWMULSU.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWMULSU interprets SEW source elements as signed vs2 by unsigned second source and writes the full 2*SEW product to vd.
Instruction input
vwmulsu.vv
Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096, vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements. Enter nonnegative SEW bit patterns; interpret vs2 as signed two’s-complement and the second source as unsigned. .vx takes low bits when XLEN>SEW or sign-extends when XLEN<SEW; x0 supplies zero. Write the full product to 2*SEW vd without accumulating old vd, saturation or vxsat change. Destination EMUL=2 requires an even start; a narrow source may overlap only its highest register, forcing mask/tail-agnostic behavior. Equal sources require equal initial values; with v0.t, vd and data sources exclude v0. Only body is shown, without definite inactive/tail values. VL=0 updates nothing; success resets vstart=0. Stages are not processor cycles.
Execution Context
OP-V encodingvwmulsu.vv
funct6
111010
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xfff0
0x0032
0x0043
0xffed
0x0065
0x0076
0xffea
0x0098
w*
w*
w*
w*
w*
w*
w*
w*
v12
0x0005
0xfff7
0x0017
0xfff5
0x0029
0xfff3
0x003b
0xfff1
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwmulsu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer signed-by-unsigned widening multiplication, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWMULSU.VV multiplies two SEW-width sources and writes the full 2*SEW product. It processes only active elements within the current vl, the second source comes from vector register vs1, and the signedness is signed vs2[i] and unsigned vs1[i].
VWMULSU.VV uses OP-V multiply-class encoding; the .vv form is selected by funct3=010.
Each active element performs vd[i] = sign_extend(vs2[i]) * zero_extend(vs1[i]), producing a 2*SEW-wide result written to widening destination vd.
The destination register group EMUL is twice the source EMUL and must satisfy the V extension legality requirements for widening destinations.
Only body elements within the current vl are processed; vm=0 uses the v0.t mask, and masked-off plus tail elements follow the current vtype policies.
This instruction is not multiply-accumulate and does not read old vd; use the matching VWMACC* instruction when accumulation is required.
Requires enabled vector state, valid vtype and support for SEW and 2*SEW; widening SEW=64 needs additional 128-bit integer element support.
With vl=0, no destination element is updated. Destination EMUL=2*LMUL must be at most 8; a narrow source overlapping the wide destination must meet the highest-end overlap constraint, and legal different-EEW overlap forces mask/tail-agnostic behavior.
Vector Execution Context
vd is a wide destination with EEW=2*SEW and EMUL=2*LMUL<=8, aligned to EMUL; vs2 and vs1 supply SEW-bit multiplicands.
32-bit OP-V: opcode=1010111, funct6=111010, funct3=010 (OPMVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1. Optional v0.t means vm=0; omission means vm=1.
Multiply signed two’s-complement vs2 by the unsigned second source and write the full 2*SEW product without accumulating old vd. Equal sources use equal initial values. Only mask-enabled vstart<=i<vl elements update; vstart>=vl (including vl=0) leaves vd unchanged.
A narrow source overlaps wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Masked vd excludes v0, which cannot supply both mask and data. Prestart stays unchanged; vma/vta govern inactive/tail preservation or permitted all ones.
RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. Success resets vstart=0 without saturation or vxsat change. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Common Usage Scenarios
Widening integer multiply
Assume enabled V/VS, valid supported e16,m1,tu,mu, supported 32-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v12=[65535,2,32768,4], v0.mask[0..3]=1111. v4=[3,3,3,3]; vd[0]=(-1)×3=-3 → 0xfffffffd. Tails retain old values; success resets vstart=0.
V standard vector extension
Assume enabled V/VS, valid supported e16,m1,tu,mu, supported 32-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v12=[65535,2,32768,4], v0.mask[0..3]=1111. v4=[3,3,3,3]; vd[0]=(-1)×3=-3 → 0xfffffffd. Tails retain old values; success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd is a wide destination with EEW=2*SEW and EMUL=2*LMUL<=8, aligned to EMUL; vs2 and vs1 supply SEW-bit multiplicands.
- 32-bit OP-V: opcode=1010111, funct6=111010, funct3=010 (OPMVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Multiply signed two’s-complement vs2 by the unsigned second source and write the full 2*SEW product without accumulating old vd. Equal sources use equal initial values. Only mask-enabled vstart<=i<vl elements update; vstart>=vl (including vl=0) leaves vd unchanged.
- A narrow source overlaps wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Masked vd excludes v0, which cannot supply both mask and data. Prestart stays unchanged; vma/vta govern inactive/tail preservation or permitted all ones.
- RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. Success resets vstart=0 without saturation or vxsat change. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
The result width is 2*SEW and destination EMUL is twice the source EMUL; this differs from single-width VMUL/VMULH.
VWMUL* writes only the product and does not read old vd as an accumulator; use VWMACC* for widening multiply-accumulate.
VWMULSU.VV uses signed vs2[i] and unsigned vs1[i] interpretation; do not confuse it with the other VWMUL, VWMULU, and VWMULSU forms.
With vm=0, masked-off destination elements follow the current mask policy; do not assume fixed zeroing or preserving.
FAQ
Does VWMULSU.VV read old vd for accumulation?
No. VWMULSU.VV writes only the product; widening multiply-accumulate semantics belong to VWMACC* instructions.