Is destination vd single-width for VWMACCSU.VV?
No. vd is a 2*SEW-wide accumulator, and the old vd value participates in the addition.
VWMACCSU.VV
RISC-V VWMACCSU.VV Instruction Details
Instruction ManualR-typeSigned-by-unsigned widening integer multiply-accumulate.
Instruction Syntax
vwmaccsu.vv vd, vs1, vs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations
Instruction Behavior
VWMACCSU.VV multiplies signed vs1 elements by unsigned vs2 elements and adds the 2*SEW product into wide vd.
Quick Understanding & Search Notes
VWMACCSU.VV is a widening multiply-accumulate instruction; old vd is the 2*SEW-wide accumulator.
The official operand order is vd, multiplier source, vs2, vm; the VX scalar is in rs1.
The product is 2*SEW wide and is added to old vd.
VWMACCSU.VV uses signed vs1 and unsigned vs2; do not swap the signedness.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vwmaccsu.vv v8, v4, v12, v0.t».
Data Storing
Understand this scenario with real code like «vwmaccsu.vv v8, v4, v12, v0.t».
Vector Operations
Understand this scenario with real code like «vwmaccsu.vv v8, v4, v12, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Old vd is the 2*SEW-wide accumulator and is overwritten.
Signedness is signed(vs1) * unsigned(vs2); do not swap it.
The destination register group is 2*SEW wide and LMUL/EMUL constraints must be legal.