Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMACC.VV
RISC-V VMACC.VV Instruction Details
Instruction ManualOPIVVAdd the low SEW bits of the vs1-by-vs2 product to old vd.
Instruction Syntax
vmacc.vv vd, vs1, vs2, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector Multiply-AddInteger Arithmetic
Instruction Behavior
VMACC.VV is a destructive RISC-V V integer multiply-add instruction. For each active element, it adds the low SEW bits of vs1[i] times vs2[i] to old vd[i] and writes the SEW-wide result back to vd[i].
VMACC.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMACC reads old vd as an accumulator, adds the low half of the SEW-by-SEW product, and writes the SEW-wide result.
Instruction input
vmacc.vv
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvmacc.vv
funct6
101101
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0xffdf
0x0131
0x0162
0x0193
0xffcb
0x01f5
0x0226
0x0257
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
acc+low*
acc+low*
acc+low*
acc+low*
acc+low*
acc+low*
acc+low*
acc+low*
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vmacc.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer , mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMACC.VV writes only active elements; integer overflow keeps the low SEW bits and does not trap.
Vector-scalar .vx forms use x[rs1], while vector-vector .vv forms use vs1.
Results are written at SEW width; high-half multiply explicitly returns the high SEW bits of the 2*SEW product.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Vector Execution Context
When reading VMACC.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Matrix Multiply
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmacc.vv v1, v2, v3 # v1[i] = v2[i]*v3[i] + v1[i]».
Signal Processing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmacc.vv v1, v2, v3 # v1[i] = v2[i]*v3[i] + v1[i]».
Convolution
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmacc.vv v1, v2, v3 # v1[i] = v2[i]*v3[i] + v1[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVV.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Single-width MAC — upper product bits discarded (unlike widening vwmacc). Use vwmacc for full precision.
Operand order: vd = vs1*vs2 + vd. vd read-write. Overflow likely at SEW=8/16.
FAQ
How does VMACC.VV handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.