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VMACC.VV

RISC-V VMACC.VV Instruction Details

Instruction ManualR-type

Add the integer product of vs1/scalar and vs2 to the old vd.

Instruction Syntax

vmacc.vv vd, vs1, vs2, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector Multiply-AddInteger Arithmetic
Related Search Terms
VMACC.VV instructionRISC-V VMACC.VVvmacc.vv syntaxvmacc.vv RVVvector integer multiply-addsigned

Instruction Behavior

VMACC.VV is a destructive RISC-V V integer multiply-add instruction. It computes vd[i] = vd[i] + vs2[i] * the second operand. Multiplication and addition produce the low SEW-width result and do not set integer exception flags.

Quick Understanding & Search Notes

VMACC.VV writes only active elements; integer overflow keeps the low SEW bits and does not trap.

Vector-scalar .vx forms use x[rs1], while vector-vector .vv forms use vs1.
Results are written at SEW width; high-half multiply explicitly returns the high SEW bits of the 2*SEW product.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VMACC.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Matrix Multiply

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmacc.vv v1, v2, v3 # v1[i] = v2[i]*v3[i] + v1[i]».

Signal Processing

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmacc.vv v1, v2, v3 # v1[i] = v2[i]*v3[i] + v1[i]».

Convolution

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmacc.vv v1, v2, v3 # v1[i] = v2[i]*v3[i] + v1[i]».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Single-width MAC — upper product bits discarded (unlike widening vwmacc). Use vwmacc for full precision.
Operand order: vd = vs1*vs2 + vd. vd read-write. Overflow likely at SEW=8/16.

FAQ

How does VMACC.VV handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.