Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMADD.VV
RISC-V VMADD.VV Instruction Details
Instruction ManualOPIVVMultiply old vd by vs1, add vs2, and overwrite vd.
Instruction Syntax
vmadd.vv vd, vs1, vs2, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector IntegerMultiply-Add
Instruction Behavior
VMADD.VV is a destructive RISC-V V single-width integer multiply-add instruction. For each active element it computes vd[i] = lowSEW(vd[i] * vs1[i]) + vs2[i] and writes the SEW-wide result to vd[i]; old vd is the first multiplicand, not an accumulator.
VMADD.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMADD reads old vd as the first multiplicand, adds its low-half product with vs1/rs1 to vs2, and writes the SEW-wide result.
Instruction input
vmadd.vv
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvmadd.vv
funct6
101001
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0xffdf
0x0131
0x0162
0x0193
0xffcb
0x01f5
0x0226
0x0257
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
oldvd*+vs2
oldvd*+vs2
oldvd*+vs2
oldvd*+vs2
oldvd*+vs2
oldvd*+vs2
oldvd*+vs2
oldvd*+vs2
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vmadd.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer first-multiplicand-overwrite integer multiply-add, old vd first multiplicand, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMADD.VV uses old vd as its first multiplicand, writes only active elements, and retains the result at SEW width.
VMADD.VV uses OP-V funct6=101001 and funct3=000; its assembly operand order is vd, vs1, vs2, vm.
Old vd is the first multiplicand and is overwritten: each active element writes lowSEW(old vd[i] * vs1[i]) + vs2[i], not the VMACC accumulator relation.
With vm=0, only body elements whose v0.t bit is 1 execute; masked-off and tail destination elements follow the current vtype vma/vta policies.
Vector Execution Context
When reading VMADD.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Polynomial Evaluation
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmadd.vv v8, v4, v6 # v8[i] = low32(v8[i] * v4[i]) + v6[i]».
Dot Product
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmadd.vv v8, v4, v6 # v8[i] = low32(v8[i] * v4[i]) + v6[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVV.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vmadd overwrites multiplicand vd; vmacc overwrites addend
Low half product may overflow-truncate—not widening
FAQ
How does VMADD.VV handle masking?
With vm=0, only body elements whose v0.t bit is 1 execute; with vm=1, all body elements within vl execute. Masked-off and tail destination elements follow the current vtype vma/vta policies.