How does VMADD.VV handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.
VMADD.VV
RISC-V VMADD.VV Instruction Details
Instruction ManualR-typeMultiply the old vd by vs1/scalar, then add vs2.
Instruction Syntax
vmadd.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector IntegerMultiply-Add
Instruction Behavior
VMADD.VV is a destructive RISC-V V integer multiply-add instruction. It computes vd[i] = vs2[i] + vd[i] * the second operand. Multiplication and addition produce the low SEW-width result and do not set integer exception flags.
Quick Understanding & Search Notes
VMADD.VV writes only active elements; integer overflow keeps the low SEW bits and does not trap.
Vector-scalar .vx forms use x[rs1], while vector-vector .vv forms use vs1.
Results are written at SEW width; high-half multiply explicitly returns the high SEW bits of the 2*SEW product.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Common Usage Scenarios
Polynomial Evaluation
Understand this scenario with real code like «vmadd.vv v8, v4, v6».
Dot Product
Understand this scenario with real code like «vmadd.vv v8, v4, v6».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vmadd overwrites multiplicand vd; vmacc overwrites addend
Low half product may overflow-truncate—not widening