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VMADD.VX

RISC-V VMADD.VX Instruction Details

Instruction ManualOPIVX

Multiply old vd by x[rs1], add vs2, and overwrite vd.

Instruction Syntax

vmadd.vx vd, rs1, vs2, vm

Operand Breakdown

vd: mask destination register, with one Boolean result bit per element.

vs2/vs1 or scalar source: compared at the current SEW.

vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.

VVector IntegerMultiply-Add

Related Search Terms

VMADD.VX instruction RISC-V VMADD.VX vmadd.vx syntax vmadd.vx encoding vector integer multiply-add VMADD scalar multiplier

Instruction Behavior

VMADD.VX is a destructive RISC-V V single-width integer multiply-add instruction. For each active element it computes vd[i] = lowSEW(vd[i] * scalarSEW(x[rs1])) + vs2[i] and writes the SEW-wide result to vd[i]; old vd is the first multiplicand, not an accumulator.

VMADD.VX Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VMADD reads old vd as the first multiplicand, adds its low-half product with vs1/rs1 to vs2, and writes the SEW-wide result.

Instruction input

vmadd.vx

vdUse v0-v31rs1Use x0-x31 or ABI namevs2Use v0-v31vmexecution mask control

VLSEWXLENold vd elements16-bit old vd first-multiplicand elementsvs2 elementscomma-separatedx11 valueXLEN=64, converted to SEW by .vx rulesv0 mask bitscontinuous 0/1 bit string

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.

OP-V encodingvmadd.vx

funct6

101001

vs2

01000

rs1

01011

funct3

100

00100

opcode

1010111

lane

old v4

0xffdf

0x0131

0x0162

0x0193

0xffcb

0x01f5

0x0226

0x0257

0x00fa

0x010b

0x011c

0x012d

0x013e

0x014f

0x0160

0x0171

oldvd*+vs2

x11

0x0013

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vmadd.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer first-multiplicand-overwrite integer multiply-add, old vd first multiplicand, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMADD.VX uses old vd as its first multiplicand; x[rs1] follows the XLEN/SEW scalar rule, and only active elements are written.

VMADD.VX uses OP-V funct6=101001 and funct3=100; its assembly operand order is vd, rs1, vs2, vm.

Old vd is the first multiplicand and is overwritten; after the XLEN/SEW scalar rule, each element computes lowSEW(old vd[i] * scalar) + vs2[i].

With vm=0, only body elements whose v0.t bit is 1 execute; masked-off and tail destination elements follow the current vtype vma/vta policies.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VMADD.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Polynomial Evaluation

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmadd.vx v8, a1, v4 # v8[i] = low32(v8[i] * x[a1]) + v4[i]».

Scale-Accumulate

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmadd.vx v8, a1, v4 # v8[i] = low32(v8[i] * x[a1]) + v4[i]».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is OPIVX.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Same overwrite as vmadd.vv, but multiplier from scalar

FAQ

How does VMADD.VX handle masking?

With vm=0, only body elements whose v0.t bit is 1 execute; with vm=1, all body elements within vl execute. Masked-off and tail destination elements follow the current vtype vma/vta policies.