Multiply old vd by x[rs1], add vs2, and overwrite vd.
Extension condition: Requires V 1.0, enabled vector state, valid vtype, and supported element widths.
VMADD.VX is a destructive V 1.0 single-width integer multiply-add instruction. Active elements compute (old vd[i] × scalarSEW(x[rs1]) + vs2[i]) mod 2^SEW and write vd[i]; old vd is the first multiplicand.
Starts from OP-V encoding fields, then shows how VMADD reads old vd as the first multiplicand, adds its low-half product with vs1/rs1 to vs2, and writes the SEW-wide result.
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
vmadd.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer first-multiplicand-overwrite integer multiply-add, old vd first multiplicand, and vd writeback. It does not model pipelines, caches, or timing.
VMADD.VX reads old vd as a multiplicand, adds vs2, and retains the low SEW result bits. Inactive/tail elements follow vma/vta.
vd supplies the old first multiplicand and receives the SEW-bit result; syntax puts vs1/rs1 before vs2. Active elements write (old vd × second source + vs2) mod 2^SEW.
rs1 selects an integer x-register: take low SEW bits when XLEN>SEW, sign-extend when XLEN<SEW; x0 supplies zero.
Require V 1.0, enabled vector state, valid vtype, and supported widths. Same-EEW source/destination overlap is allowed; masked vd cannot cover v0, and v0 cannot supply both EEW=1 mask and SEW data.
Body is vstart≤i<vl; omitting v0.t means vm=1 and including it means vm=0. Prestart is unchanged; inactive/tail follow vma/vta, with no guarantee of zero agnostic values. VL=0 or vstart≥vl updates no destination.
Assume RV32/RV64 V, enabled vector state, supported e32,m1, and VLEN≥128; after vsetivli, vl=4, vstart=0, ta/ma, with initialized sources and v0.mask=[1,0,1,1]. old v4=[10,20,30,40], x11=3, v8=[2,4,6,8] → v4=[32,policy,96,128]. policy means mask-agnostic: retain the old value or write all ones; tails are likewise not guaranteed zero.
vm=0 uses v0.t and enables only elements where vstart≤i<vl and the mask bit is 1. vm=1 is unmasked. Prestart is unchanged; inactive/tail elements follow vma/vta. With VL=0 or vstart≥vl, even tails are unchanged.