Is vd only a write destination for VNMSUB.VX?
No. This instruction is destructive: old vd is the first multiplicand.
VNMSUB.VX
RISC-V VNMSUB.VX Instruction Details
Instruction ManualOPMVXVector integer negative multiply-subtract using vd as a multiplicand.
Instruction Syntax
vnmsub.vx vd, rs1, vs2, vm
Operand Breakdown
Syntax: vnmsub.vx vd, rs1, vs2[, v0.t]; omit v0.t for vm=1 and include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101011, funct3=110.
vd is the SEW/LMUL destination and old first multiplicand. Active results are lowSEW(vs2[i]−lowSEW(scalar×old vd[i])). Same-width sources/destination may overlap; equal registers read equal initial values. Results wrap without rounding or saturation.
rs1 is an integer x register: XLEN>SEW takes low SEW bits, XLEN<SEW sign-extends; x0 supplies zero.
Only the low SEW product bits are subtracted from vs2; vd is not the old minuend used by vnmsac.
Require V 1.0, enabled vector state, and valid supported vtype. Masked vd cannot contain v0; v0 cannot supply both the EEW=1 mask and data. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
VVector IntegerMultiply-Subtract
Instruction Behavior
VNMSUB.VX computes vs2[i] - (x[rs1] * vd[i]) for active elements and writes the low SEW bits back to vd.
VNMSUB.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VNMSUB reads old vd as the first multiplicand, subtracts its low-half product with vs1/rs1 from vs2, and writes the SEW-wide result.
Instruction input
vnmsub.vx
Execution Context
The teaching model fixes LMUL=m1, vstart=0, VLEN=4096 and VLMAX=4096/16=256; enabled vector state, valid vtype and support for the selected SEW are assumed. Old vd is the first multiplicand; equal registers require equal initial values. Same-width sources/destination may overlap; masked vd cannot be v0, and v0 cannot supply mask and SEW data together. Only body elements are shown, without definite inactive/tail results; VL=0 updates no destination elements. Steps are teaching stages, not processor cycles.
OP-V encodingvnmsub.vx
funct6
101011
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0xffdf
0x0131
0x0162
0x0193
0xffcb
0x01f5
0x0226
0x0257
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
vs2-oldvd*
vs2-oldvd*
vs2-oldvd*
vs2-oldvd*
vs2-oldvd*
vs2-oldvd*
vs2-oldvd*
vs2-oldvd*
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vnmsub.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer first-multiplicand-overwrite negative multiply-subtract, old vd first multiplicand, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VNMSUB.VX is a destructive integer multiply-subtract instruction; vd participates in the multiplication and receives the result.
VNMSUB uses old vd as one multiplicand and vs2 as the minuend.
The result is truncated to SEW width and does not raise integer overflow exceptions.
vm=0 uses v0 as the execution mask; vm=1 is unmasked.
Requires V, enabled vector state, valid vtype, and supported element widths; VL=0 updates no destination elements, including tails.
With vm=0, only body elements with v0.mask[i]=1 execute; inactive/tail elements follow vma/vta and are not guaranteed to be preserved.
rs1 is an integer x register: use its low SEW bits when XLEN>SEW and sign-extend when XLEN<SEW; x0 supplies zero.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120) — 31.11.13. Vector Single-Width Integer Multiply-Add InstructionsThe RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120) — 31.5. Vector Instruction Formats; 31.10. Vector Arithmetic Instruction Formats; 31.20. Vector Instruction Listing
Vector Execution Context
Syntax: vnmsub.vx vd, rs1, vs2[, v0.t]; omit v0.t for vm=1 and include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101011, funct3=110.
vd is the SEW/LMUL destination and old first multiplicand. Active results are lowSEW(vs2[i]−lowSEW(scalar×old vd[i])). Same-width sources/destination may overlap; equal registers read equal initial values. Results wrap without rounding or saturation.
rs1 is an integer x register: XLEN>SEW takes low SEW bits, XLEN<SEW sign-extends; x0 supplies zero.
Only the low SEW product bits are subtracted from vs2; vd is not the old minuend used by vnmsac.
Require V 1.0, enabled vector state, and valid supported vtype. Masked vd cannot contain v0; v0 cannot supply both the EEW=1 mask and data. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
Common Usage Scenarios
Multiplicand-overwrite integer multiply-subtract
Assume enabled V/VS, valid m1, VLEN≥128, supported operand widths, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, old v8=[100,0,255,128], v12=[4,1,255,128], x5=3 → v8=[216,1,2,0]. Read old vd as a multiplicand, then wrap to low SEW bits. Inactive/tail values follow policy without assumed zeroing.
SEW modular arithmetic
Assume enabled V/VS, valid m1, VLEN≥128, supported operand widths, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, old v8=[100,0,255,128], v12=[4,1,255,128], x5=3 → v8=[216,1,2,0]. Read old vd as a multiplicand, then wrap to low SEW bits. Inactive/tail values follow policy without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vnmsub.vx vd, rs1, vs2[, v0.t]; omit v0.t for vm=1 and include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101011, funct3=110.
- vd is the SEW/LMUL destination and old first multiplicand. Active results are lowSEW(vs2[i]−lowSEW(scalar×old vd[i])). Same-width sources/destination may overlap; equal registers read equal initial values. Results wrap without rounding or saturation.
Semantic Check
- rs1 is an integer x register: XLEN>SEW takes low SEW bits, XLEN<SEW sign-extends; x0 supplies zero.
- Only the low SEW product bits are subtracted from vs2; vd is not the old minuend used by vnmsac.
- Require V 1.0, enabled vector state, and valid supported vtype. Masked vd cannot contain v0; v0 cannot supply both the EEW=1 mask and data. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
Pitfalls / Common Confusions
vnmsub uses old vd as one multiplicand.
vs2 is the minuend; the low SEW product bits are subtracted from it.
The low SEW bits are written and no integer overflow exception is raised.
Masked vd cannot be v0; v0 cannot supply both the EEW=1 mask and a data source.
Same-width sources/destination may overlap; equal registers must have consistent old values.