Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VNMSAC.VX
RISC-V VNMSAC.VX Instruction Details
Instruction ManualOPMVXVNMSAC.VX subtracts the low SEW bits of the GPR scalar times each vs2 element from the old vd minuend and writes the result back to vd.
Instruction Syntax
vnmsac.vx vd, rs1, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector IntegerMultiply-Accumulate
Instruction Behavior
VNMSAC.VX computes vd[i] - (x[rs1] * vs2[i]) for active elements and writes the low SEW bits back to vd.
VNMSAC.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VNMSAC reads old vd as the minuend, subtracts the low half of the SEW-by-SEW product, and writes the SEW-wide result.
Instruction input
vnmsac.vx
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvnmsac.vx
funct6
101111
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0xffdf
0x0131
0x0162
0x0193
0xffcb
0x01f5
0x0226
0x0257
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vnmsac.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer minuend-overwrite integer multiply-subtract, old vd minuend, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VNMSAC.VX is a destructive integer multiply-subtract: old vd is the minuend, each lane subtracts the low SEW product of vs2 and x[rs1] after the XLEN/SEW scalar rule, and the SEW-wide result wraps back into vd.
The official operand order is vd, multiplier source, vs2, vm; do not swap vs1/rs1 with vs2.
The OPMVX encoding uses funct6=101111, funct3=110, and OP-V opcode=1010111.
When XLEN>SEW, the low SEW bits of x[rs1] are used; when XLEN<SEW, x[rs1] is sign-extended to SEW.
The result is truncated to SEW width and does not raise integer overflow exceptions.
vm=0 uses v0 as the execution mask; vm=1 is unmasked. Only active elements from vstart through vl-1 write back; prestart stays undisturbed, while inactive and tail elements follow vtype policy.
Vector Execution Context
When reading VNMSAC.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector-scalar integer product subtraction
Understand this scenario with real code like «vnmsac.vx v8, x5, v12, v0.t».
Destructive SEW-width multiply-subtract
Understand this scenario with real code like «vnmsac.vx v8, x5, v12, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPMVX.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vnmsac subtracts the low SEW bits of the product from the old vd minuend.
Old vd is the overwritten minuend; vnmsub instead overwrites old vd as a multiplicand.
The low SEW bits are written and no integer overflow exception is raised.
FAQ
Is vd only a write destination for VNMSAC.VX?
No. VNMSAC.VX is destructive: old vd specifically participates as the minuend and is then overwritten by the result.