Is vd only a write destination for VNMSAC.VV?
No. VNMSAC.VV is destructive: old vd specifically participates as the minuend and is then overwritten by the result.
VNMSAC.VV
RISC-V VNMSAC.VV Instruction Details
Instruction ManualOPMVVVNMSAC.VV subtracts the low SEW bits of each element product from the old vd minuend and writes the SEW-wide result back to vd.
Instruction Syntax
vnmsac.vv vd, vs1, vs2, vm
Operand Breakdown
vd is the SEW/LMUL destination group and old minuend; vs2 is a same-width vector source. Same-EEW source/destination overlap is allowed; equal registers must read equal initial values.
vs1 supplies the same-lane SEW-wide multiplier; syntax order is vd, vs1, vs2, vm.
32-bit OP-V: opcode=1010111, funct6=101111, funct3=010. Active results are old vd−lowSEW(vs1[i]×vs2[i]), wrapping to low SEW bits; no saturation, vxrm use or vxsat update.
vm denotes optional v0.t, omitted for vm=1. Masked vd cannot contain v0, which cannot supply both mask and SEW data. Active body is vstart≤i<vl with mask enabled; prestart is unchanged, inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
Require V 1.0, enabled vector state and valid supported vtype; group starts align to EMUL, with EMUL≤8. Successful completion resets vstart=0; implementations may reject nonzero vstart values they cannot produce.
VVector IntegerMultiply-Accumulate
Instruction Behavior
VNMSAC.VV computes vd[i] - (vs1[i] * vs2[i]) for active elements and writes the low SEW bits back to vd.
VNMSAC.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VNMSAC reads old vd as the minuend, subtracts the low half of the SEW-by-SEW product, and writes the SEW-wide result.
Instruction input
vnmsac.vv
Execution Context
The teaching model fixes LMUL=m1, vstart=0, VLEN=4096 and VLMAX=4096/16=256; enabled vector state, valid vtype and support for the selected SEW are assumed. Old vd is the minuend; equal registers require equal initial values. Same-width sources/destination may overlap; masked vd cannot be v0, and v0 cannot supply mask and SEW data together. Only body elements are shown, without definite inactive/tail results; VL=0 updates no destination elements. Steps are teaching stages, not processor cycles.
OP-V encodingvnmsac.vv
funct6
101111
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0xffdf
0x0131
0x0162
0x0193
0xffcb
0x01f5
0x0226
0x0257
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
oldvd-low*
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vnmsac.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer minuend-overwrite integer multiply-subtract, old vd minuend, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VNMSAC.VV is a destructive integer multiply-subtract: old vd is the minuend, each lane subtracts the low SEW bits of vs1 times vs2, and the SEW-wide result wraps back into vd.
The official operand order is vd, multiplier source, vs2, vm; do not swap vs1/rs1 with vs2.
The OPMVV encoding uses funct6=101111, funct3=010, and OP-V opcode=1010111.
The result is truncated to SEW width and does not raise integer overflow exceptions.
vm=0 uses v0 as the execution mask; vm=1 is unmasked. Only active elements from vstart through vl-1 write back; prestart stays undisturbed, while inactive and tail elements follow vtype policy.
Vector Execution Context
vd is the SEW/LMUL destination group and old minuend; vs2 is a same-width vector source. Same-EEW source/destination overlap is allowed; equal registers must read equal initial values.
vs1 supplies the same-lane SEW-wide multiplier; syntax order is vd, vs1, vs2, vm.
32-bit OP-V: opcode=1010111, funct6=101111, funct3=010. Active results are old vd−lowSEW(vs1[i]×vs2[i]), wrapping to low SEW bits; no saturation, vxrm use or vxsat update.
vm denotes optional v0.t, omitted for vm=1. Masked vd cannot contain v0, which cannot supply both mask and SEW data. Active body is vstart≤i<vl with mask enabled; prestart is unchanged, inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
Require V 1.0, enabled vector state and valid supported vtype; group starts align to EMUL, with EMUL≤8. Successful completion resets vstart=0; implementations may reject nonzero vstart values they cannot produce.
Common Usage Scenarios
Vector integer product subtraction
Assume enabled V/VS, valid m1, VLEN≥128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, old vd=[100,0,255,128], vs2=[4,1,255,128], vs1=[3,3,3,3] → vd=[88,253,2,0]. Results wrap to low SEW bits; old vd is an input. Inactive/tail values follow policy without assumed zeroing.
Destructive SEW-width multiply-subtract
Assume enabled V/VS, valid m1, VLEN≥128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, old vd=[100,0,255,128], vs2=[4,1,255,128], vs1=[3,3,3,3] → vd=[88,253,2,0]. Results wrap to low SEW bits; old vd is an input. Inactive/tail values follow policy without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd is the SEW/LMUL destination group and old minuend; vs2 is a same-width vector source. Same-EEW source/destination overlap is allowed; equal registers must read equal initial values.
- vs1 supplies the same-lane SEW-wide multiplier; syntax order is vd, vs1, vs2, vm.
Semantic Check
- 32-bit OP-V: opcode=1010111, funct6=101111, funct3=010. Active results are old vd−lowSEW(vs1[i]×vs2[i]), wrapping to low SEW bits; no saturation, vxrm use or vxsat update.
- vm denotes optional v0.t, omitted for vm=1. Masked vd cannot contain v0, which cannot supply both mask and SEW data. Active body is vstart≤i<vl with mask enabled; prestart is unchanged, inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
- Require V 1.0, enabled vector state and valid supported vtype; group starts align to EMUL, with EMUL≤8. Successful completion resets vstart=0; implementations may reject nonzero vstart values they cannot produce.
Pitfalls / Common Confusions
vnmsac subtracts the low SEW bits of the product from the old vd minuend.
Old vd is the overwritten minuend; vnmsub instead overwrites old vd as a multiplicand.
The low SEW bits are written and no integer overflow exception is raised.