How does VMACC.VX handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.
VMACC.VX
RISC-V VMACC.VX Instruction Details
Instruction ManualOPMVXAdd the low SEW bits of the x[rs1]-by-vs2 product to old vd.
Instruction Syntax
vmacc.vx vd, rs1, vs2, vm
Operand Breakdown
32-bit OP-V: opcode=1010111, funct6=101101, funct3=110 (OPMVX). vd is both the old SEW accumulator and destination; syntax places vs1/rs1 before vs2.
Active elements write (old vd + x[rs1]×vs2) mod 2^SEW. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends; x0 is 0. VMADD's first multiplicand is old vd; VMACC's old vd is the addend.
Omitting v0.t gives vm=1; including it gives vm=0, enabling only masked-on body elements. Same-EEW destination/source overlap is allowed. Masked vd cannot overlap v0, and one register cannot be read as both an EEW=1 mask and SEW data.
Require V 1.0, enabled VS, valid vtype, and supported widths. Prestart stays unchanged; body is vstart≤i<vl. VL=0 or vstart≥vl updates no destination, including tails; normal completion resets vstart=0 and leaves vl unchanged.
Inactive/tail elements follow vma/vta; agnostic may retain old values or become all ones, without guaranteed zeros. The animation fixes LMUL=m1, VLEN=4096, vstart=0.
VVector IntegerMultiply-Accumulate
Instruction Behavior
VMACC.VX is a destructive RISC-V V integer multiply-add instruction. For each active element, it adds the low SEW bits of x[rs1] times vs2[i] to old vd[i] and writes the SEW-wide result back to vd[i]. When XLEN is greater than SEW it uses the low SEW bits of x[rs1]; when XLEN is smaller than SEW it sign-extends x[rs1].
VMACC.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMACC reads old vd as an accumulator, adds the low half of the SEW-by-SEW product, and writes the SEW-wide result.
Instruction input
vmacc.vx
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvmacc.vx
funct6
101101
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0xffdf
0x0131
0x0162
0x0193
0xffcb
0x01f5
0x0226
0x0257
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
acc+low*
acc+low*
acc+low*
acc+low*
acc+low*
acc+low*
acc+low*
acc+low*
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vmacc.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer addend-overwrite integer multiply-accumulate, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
Active elements compute (old vd + vs1/rs1 × vs2) mod 2^SEW; inactive/tail elements follow policy.
Vector-scalar .vx forms use x[rs1], while vector-vector .vv forms use vs1.
Single-width multiply-add keeps the low SEW result bits; widening multiply-add uses a 2×SEW accumulator, still with finite width.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Vector Execution Context
32-bit OP-V: opcode=1010111, funct6=101101, funct3=110 (OPMVX). vd is both the old SEW accumulator and destination; syntax places vs1/rs1 before vs2.
Active elements write (old vd + x[rs1]×vs2) mod 2^SEW. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends; x0 is 0. VMADD's first multiplicand is old vd; VMACC's old vd is the addend.
Omitting v0.t gives vm=1; including it gives vm=0, enabling only masked-on body elements. Same-EEW destination/source overlap is allowed. Masked vd cannot overlap v0, and one register cannot be read as both an EEW=1 mask and SEW data.
Require V 1.0, enabled VS, valid vtype, and supported widths. Prestart stays unchanged; body is vstart≤i<vl. VL=0 or vstart≥vl updates no destination, including tails; normal completion resets vstart=0 and leaves vl unchanged.
Inactive/tail elements follow vma/vta; agnostic may retain old values or become all ones, without guaranteed zeros. The animation fixes LMUL=m1, VLEN=4096, vstart=0.
Common Usage Scenarios
Element-wise integer multiply-accumulate
Assume RV32/RV64 V; enabled VS, valid vtype, VLEN≥128, and supported widths; vsetvli gives vl=4, vstart=0, ta/ma, unmasked. x10=4, x11=3; e32,m1; old v8=[10,20,30,40], v4=[2,4,6,8] → v8=[16,32,48,64]. Results use source values before writeback. Tails are not guaranteed zero; normal completion resets vstart=0.
SEW-width multiply-add
Assume RV32/RV64 V; enabled VS, valid vtype, VLEN≥128, and supported widths; vsetvli gives vl=4, vstart=0, ta/ma, unmasked. x10=4, x11=3; e32,m1; old v8=[10,20,30,40], v4=[2,4,6,8] → v8=[16,32,48,64]. Results use source values before writeback. Tails are not guaranteed zero; normal completion resets vstart=0.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V: opcode=1010111, funct6=101101, funct3=110 (OPMVX). vd is both the old SEW accumulator and destination; syntax places vs1/rs1 before vs2.
- Active elements write (old vd + x[rs1]×vs2) mod 2^SEW. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends; x0 is 0. VMADD's first multiplicand is old vd; VMACC's old vd is the addend.
Semantic Check
- Omitting v0.t gives vm=1; including it gives vm=0, enabling only masked-on body elements. Same-EEW destination/source overlap is allowed. Masked vd cannot overlap v0, and one register cannot be read as both an EEW=1 mask and SEW data.
- Require V 1.0, enabled VS, valid vtype, and supported widths. Prestart stays unchanged; body is vstart≤i<vl. VL=0 or vstart≥vl updates no destination, including tails; normal completion resets vstart=0 and leaves vl unchanged.
- Inactive/tail elements follow vma/vta; agnostic may retain old values or become all ones, without guaranteed zeros. The animation fixes LMUL=m1, VLEN=4096, vstart=0.
Pitfalls / Common Confusions
vd is both the old accumulator and the destination; retain low SEW result bits, not the full 2×SEW product.
VMACC overwrites addend vd; VMADD overwrites its first multiplicand, which is also old vd, not vs1.
Masked-off/tail elements follow vma/vta and are not guaranteed zero.