VWMACCU.VV adds the full 2*SEW product to old 2*SEW vd.
RISC-V V 1.0 widening integer multiply-accumulate using unsigned multiplicands. Add the full product to old vd, keeping low 2*SEW bits. Require enabled vector state, valid vtype and supported SEW/2*SEW. Update only mask-enabled vstart<=i<vl elements; prestart stays unchanged. Inactive/tail follow vma/vta. Wide vd is also an accumulator source and cannot overlap narrow multiplicands.
Starts from OP-V encoding fields, then shows how VWMACCU reads old 2*SEW vd as the accumulator, forms a unsigned-by-unsigned product, and writes the accumulated result.
Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096, vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements. Enter nonnegative bit patterns; interpret both multiplicands as unsigned. Read old 2*SEW vd, add the full product, and keep low 2*SEW bits; no saturation or vxsat change. Scalars first follow XLEN/SEW conversion (sign-extend if narrower, take low bits if wider); x0 supplies zero. Wide vd is an EMUL=2 accumulator source with an even start and cannot overlap narrow multiplicands; equal narrow sources require equal initial values. With v0.t, vd and data sources exclude v0. Only body is shown; inactive/tail follow vma/vta without definite displayed values. VL=0 updates nothing; success resets vstart=0. Stages are not processor cycles.
vwmaccu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening multiply-accumulate, old vd accumulator, and vd writeback. It does not model pipelines, caches, or timing.
VWMACCU.VV adds the full 2*SEW product to old 2*SEW vd.
RV32/RV64 V 1.0; enabled vector state, vill=0, supported SEW and 2*SEW. vd is a read/write accumulator with EEW=2*SEW, EMUL=2*LMUL<=8 and an aligned group start. SEW=64 needs additional 128-bit integer elements.
32-bit OP-V: opcode=1010111, funct6=111100, funct3=010 (OPMVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Syntax source order: vs1/rs1, vs2. Optional v0.t means vm=0; omission means vm=1.
Form the full 2*SEW product as unsigned × unsigned, add old vd and keep low 2*SEW bits. Wide vd is also a source; narrow multiplicands cannot overlap it, which would read one register at different EEWs. Equal source registers use equal initial values.
Compute only mask-enabled vstart<=i<vl elements. Prestart stays unchanged; inactive/tail follow vma/vta: undisturbed or agnostic (old values or all ones). Masked vd excludes v0, which cannot supply mask and data together. vstart>=vl (including vl=0) leaves all destination elements unchanged; success resets vstart=0 without saturation or vxsat change.
Assume enabled V/VS, valid e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; old v8=[1,1,1,1], v12=[255,128,1,127], v4=[255,2,128,1]. v8=[0xfe02,0x0101,unchanged,0x0080], with 16-bit results. Lane2 and tails keep old values; vxsat is unchanged, and success resets vstart=0.
Prestart stays unchanged. Inactive/tail follow vma/vta: undisturbed, or agnostic (old values or all ones, without a fixed guarantee). For this instruction, wide vd is also an accumulator source and cannot overlap narrow multiplicands.
This widening operation needs implementation support for 128-bit integer elements, beyond baseline V guarantees. Check supported SEW/2*SEW and legal register groups.