Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWMACCU.VV
RISC-V VWMACCU.VV Instruction Details
Instruction ManualR-typeVWMACCU.VV reads old 2*SEW vd as an accumulator and adds each active element's 2*SEW widening product.
Instruction Syntax
vwmaccu.vv vd, vs1, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsInteger Arithmetic
Instruction Behavior
VWMACCU.VV is a RISC-V V extension unsigned widening vector multiply-accumulate instruction. Each active element reads old 2*SEW vd[i], interprets the SEW-width multiply inputs as unsigned vs1[i] and unsigned vs2[i], adds the 2*SEW product, and writes the accumulated result back to vd[i]. With vm=0, only body elements whose v0.t bit is 1 update; masked-off and tail elements follow the current vtype policies.
VWMACCU.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWMACCU reads old 2*SEW vd as the accumulator, forms a unsigned-by-unsigned product, and writes the accumulated result.
Instruction input
vwmaccu.vv
OP-V encodingvwmaccu.vv
funct6
111100
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0xffffffdf
0x00000131
0x00000162
0x00000193
0xffffffcb
0x000001f5
0x00000226
0x00000257
v8
0xfffe
0x003a
0x004f
0xfffb
0x0079
0x008e
0xfff8
0x00b8
acc+w*
acc+w*
acc+w*
acc+w*
acc+w*
acc+w*
acc+w*
acc+w*
v12
0x0009
0xfffb
0x001f
0xfff9
0x0035
0xfff7
0x004b
0xfff5
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwmaccu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening multiply-accumulate, old vd accumulator, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWMACCU.VV is a destructive widening multiply-accumulate: vd is first read as a 2*SEW accumulator, then the 2*SEW product from unsigned vs1[i] and unsigned vs2[i] is added and written back to vd.
VWMACCU.VV uses OP-V multiply/multiply-accumulate class encoding; the vv form is selected by funct3=010.
Each active element performs vd[i] = vd[i] + zero_extend(vs1[i]) * zero_extend(vs2[i]); the result remains 2*SEW wide and is written back to the same vd accumulator.
For the .vv form, both multiply inputs come from SEW-width vector elements, while old vd is the 2*SEW-wide accumulator.
vd is the destructive destination accumulator: the old 2*SEW-wide vd value is read and overwritten. Destination EMUL is twice the source EMUL, and register-group choices must still satisfy the V extension legality rules for widening destinations and overlaps.
Only body elements within current vl are processed; vm=0 uses the v0.t mask, and masked-off plus tail elements follow current vtype policies.
Vector Execution Context
When reading VWMACCU.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vectorized Loops
Understand this scenario with real code like «vwmaccu.vv v8, v4, v12, v0.t # unsigned widening multiply-accumulate».
Integer Multiply
Understand this scenario with real code like «vwmaccu.vv v8, v4, v12, v0.t # unsigned widening multiply-accumulate».
Multi-Precision Accumulation
Understand this scenario with real code like «vwmaccu.vv v8, v4, v12, v0.t # unsigned widening multiply-accumulate».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vd is a 2*SEW-wide accumulator; this instruction reads old vd and writes the accumulated result, unlike product-only VWMUL*.
Official .vv syntax is vd, vs1, vs2, vm; the multiply-source order differs from ordinary VWMUL* pages.
The signedness is unsigned vs1[i] and unsigned vs2[i]; do not confuse it with other VWMACC/VWMACCU/VWMACCSU/VWMACCUS forms.
With vm=0, masked-off destination elements follow the current mask policy; do not assume fixed zeroing or preserving.
FAQ
How does VWMACCU.VV differ from VWMUL*?
VWMACCU.VV reads old vd as a 2*SEW accumulator and writes the accumulated result. VWMUL* writes only the full 2*SEW product and does not accumulate old vd.
Does VWMACCU.VV always process the whole vector register?
No. V instructions use vl, vtype, vstart, and the optional v0.t mask to determine active elements; inactive elements follow the current tail/mask policy.