How does VMULHU.VV differ from VWMUL*?
VMULHU.VV writes only the high SEW bits to an SEW-width vd. VWMUL* writes the full 2*SEW widening product.
VMULHU.VV
RISC-V VMULHU.VV Instruction Details
Instruction ManualOPMVVVMULHU.VV forms each active element's 2*SEW integer product and writes the product's high SEW bits.
Instruction Syntax
vmulhu.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vmulhu.vv vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=010, funct6=100100.
vd receives SEW-bit integer vector elements, not comparison-mask bits; vs2 supplies SEW-bit vector elements. vs1 supplies same-index SEW-bit vector elements; equal sources read equal initial values.
Treat both sources as unsigned; write the high SEW bits of the 2×SEW product. This is not multiply-accumulate, and does not round under vxrm or saturate.
Active elements satisfy vstart≤i<vl and either vm=1 or v0.mask[i]=1. Prestart is preserved; vma/vta govern inactive/tail preservation or permitted all-ones values. vstart≥vl (including vl=0) updates no destination elements.
Same-width source/destination overlap is legal. EEW=SEW and EMUL=LMUL; EMUL=2/4/8 groups align to their size. An ordinary masked vd cannot include v0, and v0 cannot supply both an EEW=1 mask and SEW data. Require the extension, valid supported vtype, and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. The animation fixes LMUL=m1, VLEN=4096 and vstart=0, showing body elements only; steps are not processor cycles.
VVector IntegerMultiply
Instruction Behavior
VMULHU.VV is a RISC-V V extension single-width integer vector-vector multiply instruction. Each active element reads vs2 and the second source from vector register vs1, forms a 2*SEW product, and writes the high SEW bits to vd. Both source operands are interpreted as unsigned; with vm=0, only body elements whose v0.t bit is 1 are processed, while masked-off and tail elements follow the current vtype policies.
VMULHU.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMULHU forms a 2*SEW product and writes the unsigned-by-unsigned high SEW bits to vd.
Instruction input
vmulhu.vv
Require valid vtype, enabled VS, and supported SEW; VL=0 updates nothing, including tails. An ordinary masked vd cannot be v0; v0 cannot supply both mask and SEW data. Same-width source/destination overlap is legal. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvmulhu.vv
funct6
100100
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xfffe
0x003a
0x004f
0xfffb
0x0079
0x008e
0xfff8
0x00b8
*
*
*
*
*
*
*
*
v12
0x0009
0xfffb
0x001f
0xfff9
0x0035
0xfff7
0x004b
0xfff5
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vmulhu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, the high half of a 2*SEW product integer unsigned high-half multiplication, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMULHU.VV does not write a full widening product. It forms a 2*SEW product for active elements within the current vl and writes only the high SEW bits to vd; the second source comes from vector register vs1, and both source operands are interpreted as unsigned.
VMULHU.VV uses OP-V multiply-class encoding; the .vv form is selected by funct3=010, and funct6=100100 selects VMULHU.
Each active element first forms a 2*SEW product and then writes the high SEW bits; vd remains an SEW-width ordinary vector destination, not a 2*SEW widening destination.
The second source comes from the same-lane element of vs1; this instruction is not a reduction and does not combine lanes.
Both source operands are interpreted as unsigned.
Active elements satisfy vstart≤i<vl and (vm=1 or v0.mask[i]=1); prestart is preserved, and vma/vta govern inactive/tail preservation or permitted all-ones values.
Require V 1.0, supported SEW/LMUL, vtype.vill=0 and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. vstart≥vl (including vl=0) updates no destination elements, including tails.
EEW=SEW and EMUL=LMUL; same-width source/destination overlap is legal, and EMUL=2/4/8 groups align to size. A masked vd excludes v0; v0 cannot be both EEW=1 mask and SEW data. No extra scaling, vxrm rounding or saturation.
Vector Execution Context
Syntax: vmulhu.vv vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=010, funct6=100100.
vd receives SEW-bit integer vector elements, not comparison-mask bits; vs2 supplies SEW-bit vector elements. vs1 supplies same-index SEW-bit vector elements; equal sources read equal initial values.
Treat both sources as unsigned; write the high SEW bits of the 2×SEW product. This is not multiply-accumulate, and does not round under vxrm or saturate.
Active elements satisfy vstart≤i<vl and either vm=1 or v0.mask[i]=1. Prestart is preserved; vma/vta govern inactive/tail preservation or permitted all-ones values. vstart≥vl (including vl=0) updates no destination elements.
Same-width source/destination overlap is legal. EEW=SEW and EMUL=LMUL; EMUL=2/4/8 groups align to their size. An ordinary masked vd cannot include v0, and v0 cannot supply both an EEW=1 mask and SEW data. Require the extension, valid supported vtype, and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. The animation fixes LMUL=m1, VLEN=4096 and vstart=0, showing body elements only; steps are not processor cycles.
Common Usage Scenarios
Fixed-Point
Assume enabled V/VS, valid e8,m1, VLEN≥128, vl=4, vstart=0, ta/ma and initialized sources; v0.t is used. v8=[0xff,2,0x80,7], v12=[3,3,3,3], v0.mask[0..3]=[1,0,1,1] → v4=[0x02,policy,0x01,0x00]. Both sources are unsigned. policy retains old values or permits all ones; tails are not guaranteed zero.
Fractional
Assume enabled V/VS, valid e8,m1, VLEN≥128, vl=4, vstart=0, ta/ma and initialized sources; v0.t is used. v8=[0xff,2,0x80,7], v12=[3,3,3,3], v0.mask[0..3]=[1,0,1,1] → v4=[0x02,policy,0x01,0x00]. Both sources are unsigned. policy retains old values or permits all ones; tails are not guaranteed zero.
Pre-Use Checklist
Syntax Check
- Syntax: vmulhu.vv vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=010, funct6=100100.
- vd receives SEW-bit integer vector elements, not comparison-mask bits; vs2 supplies SEW-bit vector elements. vs1 supplies same-index SEW-bit vector elements; equal sources read equal initial values.
Semantic Check
- Treat both sources as unsigned; write the high SEW bits of the 2×SEW product. This is not multiply-accumulate, and does not round under vxrm or saturate.
- Active elements satisfy vstart≤i<vl and either vm=1 or v0.mask[i]=1. Prestart is preserved; vma/vta govern inactive/tail preservation or permitted all-ones values. vstart≥vl (including vl=0) updates no destination elements.
- Same-width source/destination overlap is legal. EEW=SEW and EMUL=LMUL; EMUL=2/4/8 groups align to their size. An ordinary masked vd cannot include v0, and v0 cannot supply both an EEW=1 mask and SEW data. Require the extension, valid supported vtype, and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. The animation fixes LMUL=m1, VLEN=4096 and vstart=0, showing body elements only; steps are not processor cycles.
Pitfalls / Common Confusions
VMULHU.VV writes the high SEW bits, not the low half; use VMUL for low-half multiplication.
Both source operands are interpreted as unsigned; do not mix up the signedness combinations of VMULH, VMULHU, and VMULHSU.
With vm=0, v0.t is the execution mask; the destination value for masked-off elements is controlled by the current vtype.vma policy.
These instructions are not multiply-accumulate operations and do not read old vd as an accumulator; use VMACC/VWMACC-family instructions for accumulation.
FAQ
Does VMULHU.VV read old vd for accumulation?
No. This instruction writes only the selected high SEW bits from the current multiply; use VMACC/VWMACC-family multiply-accumulate instructions when accumulation is required.