VSMUL.VX

RISC-V VSMUL.VX Instruction Details

Instruction ManualR-type

Signed fixed-point fractional multiply with vxrm rounding and saturation.

Instruction Syntax

vsmul.vx vd, vs2, rs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations

Instruction Behavior

VSMUL.VX computes signed SEW-width products, scales by SEW-1 bits with vxrm rounding, then saturates to an SEW-width result; saturation sets vxsat.

Quick Understanding & Search Notes

VSMUL.VX is for fixed-point fractional multiplication, not ordinary integer multiply-low truncation.

The product is scaled by SEW-1 bits and rounded according to vxrm.
Out-of-range results saturate and set vxsat.
Use VMUL/VMULH forms for ordinary integer multiplication.

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «vsmul.vx v8, v12, x5, v0.t».

Data Storing

Understand this scenario with real code like «vsmul.vx v8, v12, x5, v0.t».

Vector Operations

Understand this scenario with real code like «vsmul.vx v8, v12, x5, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is a fractional multiply: the product is shifted right by SEW-1, not simply truncated.
Rounding follows vxrm; saturation sets vxsat.

FAQ

Is VSMUL.VX the same as VMUL followed by a shift?

No. VSMUL defines fixed-point rounding and saturation behavior, including vxsat on saturation.