Does VNSRL.WV round?
No. It is a narrowing right shift; use VNCLIP/VNCLIPU when fixed-point rounding and saturation are required.
VNSRL.WV
RISC-V VNSRL.WV Instruction Details
Instruction ManualOPIVV (OP-V)logical narrowing right shift from 2*SEW source elements to SEW results.
Instruction Syntax
vnsrl.wv vd, vs2, vs1, vm
Operand Breakdown
Syntax: vnsrl.wv vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101100, funct3=000.
vd is the SEW/LMUL narrow destination; vs2 is the 2*SEW/2*LMUL wide source. Logical-right-shift the unsigned wide source, then take low SEW bits, without rounding, saturation, vxrm use or vxsat updates.
vs1 supplies the same-lane SEW-wide shift count.
Only low lg2(2*SEW) count bits are used. vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. Group starts align to EMUL, EMUL≤8, and both widths must be supported.
Require V 1.0, enabled vector state and valid supported vtype. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements. Masked vd cannot contain v0, which cannot supply both mask and data.
VVector IntegerShift/Narrowing
Instruction Behavior
VNSRL.WV logically right-shifts each unsigned 2*SEW-wide source element and writes the shifted value's low SEW bits. Each lane takes its shift amount from the low lg2(2*SEW) bits of the corresponding vs1 element.
VNSRL.WV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VNSRL reads unsigned 2*SEW-wide vs2, takes the low lg2(2*SEW) shift-count bits for a logical right shift, and writes the low SEW bits to vd.
Instruction input
vnsrl.wv
Require enabled vector state, valid vtype, and support for source 2*SEW and destination SEW; VL=0 updates no destination elements. Same-start narrow-destination/wide-source overlap is legal and forces mask- and tail-agnostic behavior. Only body elements are shown; no definite inactive or tail values are invented.
Execution Context
Shift-count rule: only the low lg2(2*SEW) bits of the corresponding vs1 element are used.
The teaching model fixes LMUL=m1, vstart=0, and VLEN=4096, so VLMAX=4096/16=256. Only body elements for selected VL=8 are shown; support for source 2*SEW and destination SEW is assumed. Wide vs2 has EMUL=2 and must start at an even register; .wv vs1 cannot overlap the wide source group. No definite inactive or tail results are shown; legal different-EEW overlap forces agnostic behavior. Steps are teaching stages, not processor cycles.
OP-V encodingvnsrl.wv
funct6
101100
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00001234
0x80000040
0x000000ff
0xffffffe0
0x00010000
0x00000007
0x00001234
0x80000040
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
v12
0x0001
0x0004
0x0000
0x0008
0x0002
0x0013
0x0001
0x0004
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vnsrl.wv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW-to-SEW integer logical narrowing right shift, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VNSRL.WV shrinks wide integer results back to SEW width using a logical right shift.
Source elements are 2*SEW wide and destination elements are SEW wide.
Logical right shift shifts in zeros at the top.
This instruction does not use vxrm rounding and does not set the vxsat saturation flag.
Vector Execution Context
Syntax: vnsrl.wv vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101100, funct3=000.
vd is the SEW/LMUL narrow destination; vs2 is the 2*SEW/2*LMUL wide source. Logical-right-shift the unsigned wide source, then take low SEW bits, without rounding, saturation, vxrm use or vxsat updates.
vs1 supplies the same-lane SEW-wide shift count.
Only low lg2(2*SEW) count bits are used. vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. Group starts align to EMUL, EMUL≤8, and both widths must be supported.
Require V 1.0, enabled vector state and valid supported vtype. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements. Masked vd cannot contain v0, which cannot supply both mask and data.
Common Usage Scenarios
Wide-Source Field Extraction
Assume enabled V/VS, valid m1, VLEN≥128, supported operand widths, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v12=[4660,32768,65535,256], v4=[4,4,4,4] → v8=[35,0,255,16]. Logical-right-shift unsigned 16-bit sources by 4, then take low 8 bits. Inactive/tail follow policy without assumed zeroing.
Integer Narrowing
Assume enabled V/VS, valid m1, VLEN≥128, supported operand widths, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v12=[4660,32768,65535,256], v4=[4,4,4,4] → v8=[35,0,255,16]. Logical-right-shift unsigned 16-bit sources by 4, then take low 8 bits. Inactive/tail follow policy without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vnsrl.wv vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101100, funct3=000.
- vd is the SEW/LMUL narrow destination; vs2 is the 2*SEW/2*LMUL wide source. Logical-right-shift the unsigned wide source, then take low SEW bits, without rounding, saturation, vxrm use or vxsat updates.
Semantic Check
- vs1 supplies the same-lane SEW-wide shift count.
- Only low lg2(2*SEW) count bits are used. vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. Group starts align to EMUL, EMUL≤8, and both widths must be supported.
- Require V 1.0, enabled vector state and valid supported vtype. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements. Masked vd cannot contain v0, which cannot supply both mask and data.
Pitfalls / Common Confusions
Only the low lg2(2*SEW) bits of each vs1 shift count are used; the vncvt.x.x.w pseudo-instruction expands specifically to the .wx form with x0.