Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VNSRL.WV
RISC-V VNSRL.WV Instruction Details
Instruction ManualOPIVV (OP-V)logical narrowing right shift from 2*SEW source elements to SEW results.
Instruction Syntax
vnsrl.wv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector IntegerShift/Narrowing
Instruction Behavior
VNSRL.WV logically right-shifts each unsigned 2*SEW-wide source element and writes the shifted value's low SEW bits. Each lane takes its shift amount from the low lg2(2*SEW) bits of the corresponding vs1 element.
VNSRL.WV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VNSRL reads unsigned 2*SEW-wide vs2, takes the low lg2(2*SEW) shift-count bits for a logical right shift, and writes the low SEW bits to vd.
Instruction input
vnsrl.wv
Shift-count rule: only the low lg2(2*SEW) bits of the corresponding vs1 element are used.
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, so VLMAX=4096/16=256 and VL=8 is legal; the wide vs2 source has EMUL=2 and must start at an even register.In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvnsrl.wv
funct6
101100
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00001234
0x80000040
0x000000ff
0xffffffe0
0x00010000
0x00000007
0x00001234
0x80000040
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
v12
0x0001
0x0004
0x0000
0x0008
0x0002
0x0013
0x0001
0x0004
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vnsrl.wv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer logical narrowing right shift, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VNSRL.WV shrinks wide integer results back to SEW width using a logical right shift.
Source elements are 2*SEW wide and destination elements are SEW wide.
Logical right shift shifts in zeros at the top.
This instruction does not use vxrm rounding and does not set the vxsat saturation flag.
Vector Execution Context
When reading VNSRL.WV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Fixed-Point Scaling
Understand this scenario with real code like «vnsrl.wv v8, v12, v4, v0.t».
Precision Reduction
Understand this scenario with real code like «vnsrl.wv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVV (OP-V).
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only the low lg2(2*SEW) bits of each vs1 shift count are used; the vncvt.x.x.w pseudo-instruction expands specifically to the .wx form with x0.
FAQ
Does VNSRL.WV round?
No. It is a narrowing right shift; use VNCLIP/VNCLIPU when fixed-point rounding and saturation are required.