How is VNCLIP.WV different from VNSRL/VNSRA?
VNCLIP.WV rounds shifted-out bits using vxrm and saturates with vxsat when the result is outside the signed SEW range; VNSRL/VNSRA are narrowing shifts without saturation clipping.
VNCLIP.WV
RISC-V VNCLIP.WV Instruction Details
Instruction ManualOPIVVVNCLIP.WV is an RVV signed fixed-point narrowing clip instruction that rounds a 2*SEW source with vxrm and saturates to SEW.
Instruction Syntax
vnclip.wv vd, vs2, vs1, vm
Operand Breakdown
vd is the SEW/LMUL narrow destination group; vs2 is the 2*SEW/2*LMUL wide source group. Group starts must align, EMUL≤8, and source/destination widths must be supported.
The count comes from the same-lane SEW-wide vs1 element; only its low lg2(2*SEW) bits are used. Apply the vxrm rnu/rne/rdn/rod rounded right shift, then saturate to signed SEW; active saturation sets sticky vxsat.
vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. One register cannot supply sources at multiple EEWs.
vm denotes optional v0.t: vm=0 selects active body elements, omitted for vm=1. A masked vd cannot contain v0; v0 cannot supply both mask and data. Body satisfies vstart≤i<vl; vstart≥vl (including vl=0) updates no destination elements.
Require V 1.0, enabled vector state, and valid supported vtype. The example assumes LMUL=m1, SEW=16, vl=8, vstart=0, and initialized sources, vxrm, and v0.
VVector Fixed-PointNarrowing/Clip
Instruction Behavior
VNCLIP.WV reads each active 2*SEW-wide vs2 element, performs a fixed-point rounded right shift using a shift amount from the same-lane vs1 element, then clips into the signed SEW range and writes the SEW-wide vd result; any active saturation sets sticky vxsat.
VNCLIP.WV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VNCLIP reads 2*SEW-wide vs2, rounded-shifts right using the shift amount and vxrm, saturates into a signed SEW-wide vd result, and sets vxsat on saturation.
Instruction input
vnclip.wv
Require enabled vector state, valid vtype, and support for source 2*SEW and destination SEW; VL=0 updates no destination elements. Same-start narrow-destination/wide-source overlap is legal and forces mask- and tail-agnostic behavior. Only body elements are shown; no definite inactive or tail values are invented.
Execution Context
The teaching model fixes LMUL=m1, vstart=0, and VLEN=4096, so VLMAX=4096/16=256. Only body elements for selected VL=8 are shown; support for source 2*SEW and destination SEW is assumed. Wide vs2 has EMUL=2 and must start at an even register; .wv vs1 cannot overlap the wide source group. No definite inactive or tail results are shown; legal different-EEW overlap forces agnostic behavior. Steps are teaching stages, not processor cycles.
OP-V encodingvnclip.wv
funct6
101111
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00000123
0x80000010
0x000000ff
0x7fffffff
0xffffffe0
0x00000007
0x00000123
0x80000010
clip>>
clip>>
clip>>
clip>>
clip>>
clip>>
clip>>
clip>>
v12
0x0001
0x0004
0x0000
0x0008
0x0002
0x0013
0x0001
0x0004
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
lane saturation
0
0
0
1
0
0
0
1
vxsat[0] is one sticky CSR bit: its prior value is 0, active lanes saturate in this instruction, and its state after writeback is 1. The lane-saturation row above only shows which lanes trigger this instruction's set condition.
Current step
Show OP-V 32-bit encoding fields
vnclip.wv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW-to-SEW narrowing clip integer signed narrowing clip, vxrm fixed-point rounding, and vd writeback; this example sets sticky vxsat. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VNCLIP.WV narrows a wide fixed-point intermediate back to SEW width: it applies a rounded right shift using the shift amount and vxrm, clips to the signed destination range, and records active-element saturation in vxsat.
The WV form uses OP-V encoding; funct6=101111, and funct3=000 selects the .wv operand form.
Source vs2 elements are interpreted at 2*SEW width and destination vd elements are SEW wide; the shift amount comes from the same-lane vs1 element. Only the low lg2(2*SEW) count bits are used.
Rounding is controlled by vxrm mode rnu, rne, rdn, or rod, followed by saturation into the signed destination range.
Only body elements within current vl and enabled by the execution mask participate; elements disabled by v0.t do not participate in this instruction's vxsat decision.
Require enabled vector state, valid vtype, and support for source 2*SEW and destination SEW. Groups must satisfy EMUL, alignment, and overlap constraints; legal different-EEW source/destination overlap forces mask- and tail-agnostic behavior.
The example assumes LMUL=m1, supported SEW=16, vl=8, vstart=0, and initialized sources, vxrm, and v0; vm denotes optional v0.t, omitted for vm=1. VL=0 updates no destination elements; vxsat retains its prior value unless active saturation sets it to 1.
Vector Execution Context
vd is the SEW/LMUL narrow destination group; vs2 is the 2*SEW/2*LMUL wide source group. Group starts must align, EMUL≤8, and source/destination widths must be supported.
The count comes from the same-lane SEW-wide vs1 element; only its low lg2(2*SEW) bits are used. Apply the vxrm rnu/rne/rdn/rod rounded right shift, then saturate to signed SEW; active saturation sets sticky vxsat.
vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. One register cannot supply sources at multiple EEWs.
vm denotes optional v0.t: vm=0 selects active body elements, omitted for vm=1. A masked vd cannot contain v0; v0 cannot supply both mask and data. Body satisfies vstart≤i<vl; vstart≥vl (including vl=0) updates no destination elements.
Require V 1.0, enabled vector state, and valid supported vtype. The example assumes LMUL=m1, SEW=16, vl=8, vstart=0, and initialized sources, vxrm, and v0.
Common Usage Scenarios
Fixed-point result narrowing
Understand this scenario with real code like «vnclip.wv v8, v12, v4, v0.t».
Vector DSP scaled output
Understand this scenario with real code like «vnclip.wv v8, v12, v4, v0.t».
Wide-to-narrow conversion that needs a saturation flag
Understand this scenario with real code like «vnclip.wv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- vd is the SEW/LMUL narrow destination group; vs2 is the 2*SEW/2*LMUL wide source group. Group starts must align, EMUL≤8, and source/destination widths must be supported.
- The count comes from the same-lane SEW-wide vs1 element; only its low lg2(2*SEW) bits are used. Apply the vxrm rnu/rne/rdn/rod rounded right shift, then saturate to signed SEW; active saturation sets sticky vxsat.
Semantic Check
- vd may overlap wide vs2 only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot overlap the wide source group. One register cannot supply sources at multiple EEWs.
- vm denotes optional v0.t: vm=0 selects active body elements, omitted for vm=1. A masked vd cannot contain v0; v0 cannot supply both mask and data. Body satisfies vstart≤i<vl; vstart≥vl (including vl=0) updates no destination elements.
- Require V 1.0, enabled vector state, and valid supported vtype. The example assumes LMUL=m1, SEW=16, vl=8, vstart=0, and initialized sources, vxrm, and v0.
Pitfalls / Common Confusions
VNCLIP.WV uses 2*SEW-wide vs2 elements and writes SEW-wide vd results; do not read it as an ordinary single-width shift.
Rounding comes from the V extension fixed-point CSR vxrm, not floating-point frm.
VNCLIP clips into the signed range; sticky vxsat is set only when an active element saturates. Mixed-EEW source and destination groups may overlap only at the same lowest register; other group constraints depend on the current vtype.
FAQ
When does VNCLIP.WV set vxsat?
This instruction sets sticky vxsat when any active element has a rounded shifted result outside the signed SEW range and is clipped. Elements disabled by v0.t do not participate in that decision.