Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSETVLI
RISC-V VSETVLI Instruction Details
Instruction ManualI-typeConfigure vl/vtype from rs1/rd AVL rules and vtypei, then write the selected vl to rd
Instruction Syntax
vsetvli rd, rs1, vtypei
Operand Breakdown
rd: receives the selected new vl; with rd=x0 it is not saved to an integer register.
rs1: supplies AVL, with special rs1=x0 forms for requesting VLMAX or preserving the current vl.
vtypei: encodes SEW, LMUL, tail policy, and mask policy.
VVector OperationsVector Config
Instruction Behavior
VSETVLI is an RVV vector-configuration instruction. It uses the OP-V opcode space with funct3=111 and derives AVL from the rs1/rd combination. Ordinary AVL form: rs1 is nonzero, AVL=x[rs1]. VLMAX request form: rs1=x0, rd must be nonzero. Keep current vl form: rd=x0, rs1=x0, valid only when the new SEW/LMUL ratio leaves VLMAX unchanged and prior vtype.vill=0. vtypei encodes SEW, LMUL, vta, and vma; the selected vl is written to rd, with rd=x0 discarding the GPR write. Unsupported vtype follows the official vill and vl=0 result.
VSETVLI Decode And Execute Animation
Decode the vset fields, derive AVL and vtype, then show the architectural vl/vtype/rd update.
Step 1 / 6
Encoding
VSETVLI is an OP-V configuration instruction. This step shows the opcode, funct3, and the fields carrying AVL/vtype information.
Instruction input
vsetvli
Scope: this animation shows only the ISA-visible vl/vtype selection rules from the V extension. Demo VLMAX and mid-range vl choice are educational inputs, not claims about a processor's VLEN, ELEN, support matrix, or OS handling.
Encoding fieldsvsetvli / OP-V
31
fixed
0
30..20
vtypei
00011010000
19..15
rs1
01010
14..12
funct3
111
11..7
rd
00101
6..0
opcode
1010111
asm
form
VSETVLI
Configuration data path
AVL source
x10
AVL
40
VLMAX
16
selected vl
16
vtype
e32, m1, ta, ma
x5
16
Current configuration summary
vl result
16
policy
ta/ma
vl selection result
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
The demo selects vl=16 from AVL=40 and VLMAX=16. Green cells show the body element range after configuration.
Quick Understanding & Search Notes
VSETVLI is the most common RVV setup instruction. It derives AVL from the rs1/rd combination, derives SEW, LMUL, vta, and vma from vtypei, selects vl against the implementation VLMAX, and writes vl to rd. Later vector instructions use that vl/vtype for active elements, tail policy, and masked-off policy.
The OP-V opcode is 1010111 with funct3=111; vtypei encodes vma, vta, vsew, and vlmul.
Ordinary AVL form: rs1 nonzero, AVL=x[rs1]. VLMAX request form: rs1=x0, rd must be nonzero. Keep current vl form: rd=x0, rs1=x0.
The selected vl is written to rd; rd=x0 only discards the integer-register write and does not prevent vl/vtype updates.
Unsupported vtype follows the official vill and vl=0 result; the page animation does not model an implementation-specific support matrix.
Vector Execution Context
When reading VSETVLI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma # configure SEW=32, LMUL=1, write vl to t0».
Data Storing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma # configure SEW=32, LMUL=1, write vl to t0».
Vector Operations
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma # configure SEW=32, LMUL=1, write vl to t0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
VLMAX request form: rs1=x0, rd!=x0. Keep current vl form: rd=x0, rs1=x0.
V 1.0 assembly should explicitly spell ta/tu and ma/mu.
Unsupported vtype follows the official vill and vl=0 result.
FAQ
Does vsetvli x0, x0, ... request VLMAX?
No. Keep current vl form: rd=x0, rs1=x0. VLMAX request form: rs1=x0, rd must be nonzero.
Does vsetvli set vl directly from vtypei?
No. vtypei selects SEW/LMUL and policy bits; vl is selected from AVL, VLMAX, and the official vector-length rules.