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VSETVLI

RISC-V VSETVLI Instruction Details

Instruction ManualI-type

Set vtype and vl: rd receives new vl, rs1/rd encoding determines AVL, and vtypei selects SEW, LMUL, and tail/mask policy

Instruction Syntax

vsetvli rd, rs1, vtypei
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
VVector OperationsVector Config
Related Search Terms
VSETVLI instructionRISC-V VSETVLIvsetvli syntaxvsetvli encodingvsetvli Vvsetvli vectorvector length and vtype setup

Instruction Encoding

31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode

VSETVLI uses opcode 1010111 (0x57), funct3 111. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.

Format: I-type
opcode: 1010111 (0x57)
funct3: 111 (0x7)

Instruction Behavior

VSETVLI is an RVV configuration instruction: it determines AVL from the rs1/rd encoding, sets SEW, LMUL, vta, and vma from vtypei, and writes the new vl to rd. If rs1!=x0, AVL=x[rs1]; if rs1=x0 and rd!=x0, AVL=~0 to request VLMAX; if rs1=x0 and rd=x0, the current vl is used and the form is valid only when the new SEW/LMUL ratio does not change VLMAX.

Quick Understanding & Search Notes

VSETVLI derives AVL from the rs1/rd encoding, sets SEW, LMUL, and tail/mask policy from vtypei, then writes the selected new vl to rd. Modern assembly should spell out ta/tu and ma/mu.

If rs1!=x0, AVL is x[rs1]; if rs1=x0 and rd!=x0, AVL is ~0 to request VLMAX.
If rs1=x0 and rd=x0, the existing vl is used; this form is valid only when the new SEW/LMUL ratio does not change VLMAX.
An unsupported vtype sets vill and vl=0; implementations may alternatively trap.
RISC-V Unprivileged ISA Manual, V Extension

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma # set vl for 32-bit elements».

Data Storing

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma # set vl for 32-bit elements».

Vector Operations

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma # set vl for 32-bit elements».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

rs1=x0 with rd!=x0 requests VLMAX; rd=x0,rs1=x0 is the special form that preserves current vl.
V 1.0 assembly should explicitly spell ta/tu and ma/mu.
Unsupported vtype sets vill and vl=0; an implementation may also trap.

FAQ

Does vsetvli x0, x0 always set VLMAX?

No. rs1=x0 and rd=x0 preserves the existing vl; requesting VLMAX requires rd!=x0.

Why write ta/ma explicitly?

V 1.0 assembly syntax requires explicit tail and mask policy flags to avoid old-default ambiguity.