How does VSETIVLI differ from VSETVLI?
VSETIVLI takes AVL from a 5-bit uimm; VSETVLI usually takes AVL from rs1 and has rs1=x0 special forms. Both use vtypei to configure vtype.
VSETIVLI
RISC-V VSETIVLI Instruction Details
Instruction ManualOP-V vector configuration (immediate AVL)Configure vl/vtype from a 5-bit immediate AVL and vtypei, then write the selected vl to rd
Instruction Syntax
vsetivli rd, uimm, vtypei
Operand Breakdown
rd is a GPR; uimm is a zero-extended 5-bit AVL (0–31), including valid zero; vtypei specifies SEW, LMUL, ta/tu and ma/mu.
32-bit OP-V: bits[31:30]=11, bits[29:20]=vtypei[9:0], bits[19:15]=uimm, funct3=111 and opcode=1010111. The unsigned immediate is not sign-extended as an ordinary I-type operand.
VLMAX=LMUL×VLEN/SEW. AVL≤VLMAX selects vl=AVL; VLMAX<AVL<2×VLMAX allows ceil(AVL/2)≤vl≤VLMAX; AVL≥2×VLMAX selects VLMAX. The same implementation is deterministic for equal AVL/VLMAX inputs.
rd=x0 only discards GPR writeback; uimm still supplies AVL, with no rs1=x0 special form.
Require V 1.0 and enabled vector state; vset does not depend on old vtype. Successful completion updates vl/vtype and clears vstart. Unsupported vtype sets vill, zeroes other vtype bits and vl; an implementation may instead trap to emulate illegal configurations.
VVector Configurationvset Instructions
Instruction Behavior
VSETIVLI is the immediate-AVL form of VSETVLI. It uses a 5-bit zero-extended uimm as AVL and uses vtypei to encode SEW, LMUL, vta, and vma. Hardware selects the new vl from AVL and VLMAX, updates vl/vtype, and writes the selected vl to rd; rd=x0 only discards the GPR write. Successful execution resets vstart to zero.
VSETIVLI Decode And Execute Animation
Decode the vset fields, derive AVL and vtype, then show the architectural vl/vtype/rd update.
Step 1 / 6
Encoding
VSETIVLI is an OP-V configuration instruction. This step shows the opcode, funct3, and the fields carrying AVL/vtype information.
Instruction input
vsetivli
Execution Context
Scope: this animation shows only the ISA-visible vl/vtype selection rules from the V extension. Demo VLMAX and mid-range vl choice are educational inputs, not claims about a processor's VLEN, ELEN, support matrix, or OS handling.
Encoding fieldsvsetivli / OP-V
31..30
fixed
11
29..20
vtypei
0011010000
19..15
uimm
01000
14..12
funct3
111
11..7
rd
00101
6..0
opcode
1010111
asm
form
VSETIVLI
Configuration data path
AVL source
uimm[4:0]
AVL
8
VLMAX
16
selected vl
8
vtype
e32, m1, ta, ma
x5
not written back
vstart
3
Current configuration summary
vl result
8
policy
ta/ma
vl selection result
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
The demo selects vl=8 from AVL=8 and VLMAX=16. Green cells show the body element range after configuration.
Assume V and the required vector state are enabled. This demo shows successful completion (using the vill path for unsupported configurations); an implementation may instead trap on illegal vtype to support emulation. Numeric AVL input is limited to exact nonnegative safe integers in an RV64 teaching context. Steps are explanatory, not hardware cycles.
Quick Understanding & Search Notes
VSETIVLI places AVL directly in the instruction as a 5-bit immediate, which is useful for small constant element counts. It still configures SEW, LMUL, vta, and vma through vtypei, then updates vl/vtype and can save the new vl in rd.
uimm is a 5-bit zero-extended AVL in the range 0 through 31.
The encoding fixes bits[31:30]=11 and places vtypei[9:0] in bits[29:20]; it encodes vma, vta, vsew, and vlmul.
rd=x0 does not save the new vl, but vl/vtype are still updated by the instruction.
Unsupported configurations set vill=1 and zero other vtype bits and vl; implementations may instead trap on illegal vtype for emulation.
Vector Execution Context
rd is a GPR; uimm is a zero-extended 5-bit AVL (0–31), including valid zero; vtypei specifies SEW, LMUL, ta/tu and ma/mu.
32-bit OP-V: bits[31:30]=11, bits[29:20]=vtypei[9:0], bits[19:15]=uimm, funct3=111 and opcode=1010111. The unsigned immediate is not sign-extended as an ordinary I-type operand.
VLMAX=LMUL×VLEN/SEW. AVL≤VLMAX selects vl=AVL; VLMAX<AVL<2×VLMAX allows ceil(AVL/2)≤vl≤VLMAX; AVL≥2×VLMAX selects VLMAX. The same implementation is deterministic for equal AVL/VLMAX inputs.
rd=x0 only discards GPR writeback; uimm still supplies AVL, with no rs1=x0 special form.
Require V 1.0 and enabled vector state; vset does not depend on old vtype. Successful completion updates vl/vtype and clears vstart. Unsupported vtype sets vill, zeroes other vtype bits and vl; an implementation may instead trap to emulate illegal configurations.
Common Usage Scenarios
Stripmining Loop
Assume RV32/RV64 V, enabled vector state, supported e32,m1,ta,ma and VLEN=256, giving VLMAX=8. uimm=8: successful execution of the example sets vl=t0=8 and vstart=0, without element masking.
Vector Length
Assume RV32/RV64 V, enabled vector state, supported e32,m1,ta,ma and VLEN=256, giving VLMAX=8. uimm=8: successful execution of the example sets vl=t0=8 and vstart=0, without element masking.
Pre-Use Checklist
Syntax Check
- rd is a GPR; uimm is a zero-extended 5-bit AVL (0–31), including valid zero; vtypei specifies SEW, LMUL, ta/tu and ma/mu.
- 32-bit OP-V: bits[31:30]=11, bits[29:20]=vtypei[9:0], bits[19:15]=uimm, funct3=111 and opcode=1010111. The unsigned immediate is not sign-extended as an ordinary I-type operand.
Semantic Check
- VLMAX=LMUL×VLEN/SEW. AVL≤VLMAX selects vl=AVL; VLMAX<AVL<2×VLMAX allows ceil(AVL/2)≤vl≤VLMAX; AVL≥2×VLMAX selects VLMAX. The same implementation is deterministic for equal AVL/VLMAX inputs.
- rd=x0 only discards GPR writeback; uimm still supplies AVL, with no rs1=x0 special form.
- Require V 1.0 and enabled vector state; vset does not depend on old vtype. Successful completion updates vl/vtype and clears vstart. Unsupported vtype sets vill, zeroes other vtype bits and vl; an implementation may instead trap to emulate illegal configurations.
Pitfalls / Common Confusions
AVL is a 5-bit zero-extended immediate, range 0-31.
Unsupported vtype follows the official vill and vl=0 result; software should check vill.
vsetivli/vsetvli assembly should state ta/tu and ma/mu explicitly.
FAQ
Is uimm=0 illegal?
No. uimm=0 means AVL=0, which selects vl=0 under the official vector-length rules.