Does VSETIVLI only write CSRs?
No. It selects vl according to AVL and vtype rules, updates vtype, and writes the new vl to rd.
VSETIVLI
RISC-V VSETIVLI Instruction Details
Instruction ManualI-typeSet vl/vtype using immediate AVL and vtypei.
Instruction Syntax
vsetivli rd, uimm, vtypei
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
VVector Configurationvset Instructions
Related Search Terms
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
VSETIVLI uses opcode 1010111 (0x57), funct3 111. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 1010111 (0x57)
funct3: 111 (0x7)
Instruction Behavior
VSETIVLI selects new vl and vtype from a 5-bit unsigned immediate AVL and the encoded vtypei, then writes the new vl to rd.
Quick Understanding & Search Notes
VSETIVLI is an RVV configuration instruction that determines vl and vtype for following vector instructions.
AVL comes from a 5-bit zero-extended immediate field.
The resulting vl is written to rd; with rd=x0 it is not kept in an integer register.
The vtypei immediate encodes SEW, LMUL, tail policy, and mask policy.
Common Usage Scenarios
Stripmining Loop
Understand this scenario with real code like «vsetivli t0, 8, e32, m1, ta, ma».
Vector Length
Understand this scenario with real code like «vsetivli t0, 8, e32, m1, ta, ma».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
AVL is a 5-bit zero-extended immediate, range 0-31.
An unsupported vtype normally sets vill and vl=0; software should check vill.
vsetivli/vsetvli assembly should state ta/tu and ma/mu explicitly.