Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSETIVLI
RISC-V VSETIVLI Instruction Details
Instruction ManualI-typeConfigure vl/vtype from a 5-bit immediate AVL and vtypei, then write the selected vl to rd
Instruction Syntax
vsetivli rd, uimm, vtypei
Operand Breakdown
rd: receives the selected new vl.
uimm: 5-bit zero-extended AVL immediate.
vtypei: encodes SEW, LMUL, tail policy, and mask policy.
VVector Configurationvset Instructions
Instruction Behavior
VSETIVLI is the immediate-AVL form of VSETVLI. It uses a 5-bit zero-extended uimm as AVL and uses vtypei to encode SEW, LMUL, vta, and vma. Hardware selects the new vl from AVL and VLMAX, updates vl/vtype, and writes the selected vl to rd; rd=x0 only discards the GPR write.
VSETIVLI Decode And Execute Animation
Decode the vset fields, derive AVL and vtype, then show the architectural vl/vtype/rd update.
Step 1 / 6
Encoding
VSETIVLI is an OP-V configuration instruction. This step shows the opcode, funct3, and the fields carrying AVL/vtype information.
Instruction input
vsetivli
Scope: this animation shows only the ISA-visible vl/vtype selection rules from the V extension. Demo VLMAX and mid-range vl choice are educational inputs, not claims about a processor's VLEN, ELEN, support matrix, or OS handling.
Encoding fieldsvsetivli / OP-V
31..30
fixed
11
29..20
vtypei
0011010000
19..15
uimm
01000
14..12
funct3
111
11..7
rd
00101
6..0
opcode
1010111
asm
form
VSETIVLI
Configuration data path
AVL source
uimm[4:0]
AVL
8
VLMAX
16
selected vl
8
vtype
e32, m1, ta, ma
x5
8
Current configuration summary
vl result
8
policy
ta/ma
vl selection result
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
The demo selects vl=8 from AVL=8 and VLMAX=16. Green cells show the body element range after configuration.
Quick Understanding & Search Notes
VSETIVLI places AVL directly in the instruction as a 5-bit immediate, which is useful for small constant element counts. It still configures SEW, LMUL, vta, and vma through vtypei, then updates vl/vtype and can save the new vl in rd.
uimm is a 5-bit zero-extended AVL in the range 0 through 31.
vtypei matches vsetvli and encodes vma, vta, vsew, and vlmul.
rd=x0 does not save the new vl, but vl/vtype are still updated by the instruction.
Unsupported vtype follows the official vill and vl=0 result.
Vector Execution Context
When reading VSETIVLI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Stripmining Loop
Understand this scenario with real code like «vsetivli t0, 8, e32, m1, ta, ma # configure up to 8 elements».
Vector Length
Understand this scenario with real code like «vsetivli t0, 8, e32, m1, ta, ma # configure up to 8 elements».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
AVL is a 5-bit zero-extended immediate, range 0-31.
Unsupported vtype follows the official vill and vl=0 result; software should check vill.
vsetivli/vsetvli assembly should state ta/tu and ma/mu explicitly.
FAQ
How does VSETIVLI differ from VSETVLI?
VSETIVLI takes AVL from a 5-bit uimm; VSETVLI usually takes AVL from rs1 and has rs1=x0 special forms. Both use vtypei to configure vtype.
Is uimm=0 illegal?
No. uimm=0 means AVL=0, which selects vl=0 under the official vector-length rules.